urukul: support low frequency (10 MHz) ref clock

[jordens]

• check loop filter
• extend the cpld interface and device_db arguments
• urukul gateware changes: make the divider configurable quartiq/urukul#3

[jordens]

Based on a quick check this seems to work at 10 MHz. Someone would need to check how good or bad the loop filter is and what the optimal values are for 10 MHz and pll_n=100.