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make the divider configurable #3

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4 of 6 tasks
jordens opened this issue Aug 14, 2018 · 1 comment
Closed
4 of 6 tasks

make the divider configurable #3

jordens opened this issue Aug 14, 2018 · 1 comment
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jordens commented Aug 14, 2018 •
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  • useful for low frequency (e.g. 10 MHz, 100 MHz) reference with AD9910 where divide-by-four is not needed and detrimental
  • also needed for bypassing the PLL at 1 GHz direct
  • check loop filter/Icp usability at low frequencies

Roadmap

  • add CFG bits for 1/2/4 division
  • document old hardware behavior, new behavior
  • expose in urukul coredevice driver
  • test 1 GHz divide-by-1 PLL bypass

Not in scope:

  • test 10 MHz divide-by-1 100x PLL (assuming loop filter/Icp usability)
  • test 100 MHz divide-by-2 20x PLL (assuming loop filter/Icp usability)
@jordens jordens mentioned this issue Sep 25, 2018
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@jordens jordens mentioned this issue Nov 1, 2018
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@jordens jordens self-assigned this Jan 2, 2019
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jordens commented Jan 2, 2019

1 GHz use case funded by Hosten/IST

jordens added a commit that referenced this issue Jan 15, 2019
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cfg: add div to configure clock divider
7085200 
Keeping the two bits at 0 will ensure backwards compatible default operation.
Other settings force the divider to the respective value.

* 0: en_ad9910: divide-by-4, ~en_ad9910: divide-by-1
* 1: divide-by-1
* 2: divide-by-2
* 3: divide-by-4

c.f. #3
@jordens jordens mentioned this issue Jan 15, 2019
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@jordens jordens closed this as completed Jan 28, 2019
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