You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Currently IO_UPDATE targets all four channels. This means that with the auto-clear phase accumulator bit set it will reset all four phase accumulators. To implement independent absolute (and tracking/coherent) phase updates, in addition to the profile register, the configuration register needs to be set twice for each update.
Implement per-channel gating in CPLD gateware (quartiq/urukul#3) and use in the coredevice driver to place the IO_UPDATE pulse in the channel-gated window of the SPI transfer.
The changes in the CPLD gateware and the coredevice driver can be made backwards compatible.
Currently IO_UPDATE targets all four channels. This means that with the auto-clear phase accumulator bit set it will reset all four phase accumulators. To implement independent absolute (and tracking/coherent) phase updates, in addition to the profile register, the configuration register needs to be set twice for each update.
Implement per-channel gating in CPLD gateware (quartiq/urukul#3) and use in the coredevice driver to place the IO_UPDATE pulse in the channel-gated window of the SPI transfer.
The changes in the CPLD gateware and the coredevice driver can be made backwards compatible.
c.f. #1143 for absolute phase mode
The text was updated successfully, but these errors were encountered: