test/coredevice: Add input gate/timestamp test #1136
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dnadlinger
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artiq/test/coredevice/test_rtio.py
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| def run(self): | ||
| # Make sure there are no leftover events. | ||
| self.core.break_realtime() | ||
| self.loop_in.count() |
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There may be leftover events because of the very bug you are testing against (due to the gateware latency in the timestamp counter to gate path, the timeout - referenced to the timestamp counter - is too small and the kernel thinks the gateware has closed the gate when it has not). Use core.reset() instead.
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| self.core.reset() | ||
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| # Determine loop delay. | ||
| self.core.break_realtime() |
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reset() already does break_realtime().
| if not (gate_start_mu < in_mu < gate_end_mu): | ||
| raise PulseNotReceived("Input event should occur during gate") | ||
| if not (-2 < (in_mu - out_mu - loop_delay_mu) < 2): | ||
| raise PulseNotReceived("Loop delay should not change") |
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What about IncorrectPulseTiming?
| if in_mu < 0: | ||
| raise PulseNotReceived("No input event") | ||
| if not (gate_start_mu < in_mu < gate_end_mu): | ||
| raise PulseNotReceived("Input event should occur during gate") |
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Right now there is an uncompensated latency offset between the gate and the input. So, the received timestamps can be slightly outside the gate. This offset also causes the pulse not to be received above.
| self.loop_in.gate_rising_mu(24) | ||
| gate_end_mu = now_mu() | ||
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| out_mu = gate_start_mu - loop_delay_mu |
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+ 3*8 compensates for latency offset (then the pulse arrives in the middle of the gate).
Expected to be broken based on local tests.