Join GitHub today
GitHub is home to over 20 million developers working together to host and review code, manage projects, and build software together.
Latest commit 84b3e3c
Oct 10, 2014
This will ease editing the documentation. For now only a HTML output is generated. Signed-off-by: Michael Walle <firstname.lastname@example.org>
|Failed to load latest commit information.|
LatticeMico32 ============= LatticeMico32 is a soft processor originally developed by Lattice Semiconductor . It was released under an open IP core license. This is a fork of the original sources distributed by Lattice. It includes new features, bugfixes and support for other FPGA devices. All additional features are BSD-licensed. Please note that this is only the processor core, not a complete SoC. Original Features ================= * 32-bit RISC architecture * Six stage pipeline * Two Wishbone bus interfaces for instruction and data * 32 external interrupts * 32 general purpose registers * Instruction and data caches * Embedded instruction ROM and data RAM support Added Features ============== * MMU support * Non-privileged user-mode support * JTAG support for Xilinx Spartan-6 devices * Test bench (using Icarus Verilog ) * Replaced device specific primitives with generic verilog modules * Unit tests shared with QEMU Reference Manual ================ You can find the reference manual at . Getting Started =============== This repository provides all you need to simulate programs with the system test bench. Try it, by typing make sim_hello_world in the test/ directory. For an example of a larger project which uses this core, see MiSoC . References ==========  http://www.latticesemi.com  http://www.latticesemi.com/documents/doc20890x45.pdf  http://iverilog.icarus.com  http://github.com/milkymist/misoc