Emit `default_nettype none.

m-labs · Sep 10, 2018 · 2a7e33e · 2a7e33e
1 parent cff127d
commit 2a7e33e
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
@@ -204,7 +204,8 @@ def _printheader(f, ios, name, ns, attr_translate,
     targets = list_targets(f) | special_outs
     wires, comb_regs = _list_comb_wires_regs(f)
     wires |= special_outs
-    r = "module " + name + "(\n"
+    r = "`default_nettype none\n\n"
+    r += "module " + name + "(\n"
     firstp = True
     for sig in sorted(ios, key=lambda x: x.duid):
         if not firstp: