sayma_rtm: add ref_lo_clk_sel

m-labs · Jun 12, 2018 · 5947224 · 5947224
1 parent 4cb07f1
commit 5947224
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/migen/build/platforms/sinara/sayma_rtm.py b/migen/build/platforms/sinara/sayma_rtm.py
@@ -38,6 +38,7 @@
     ("clk_src_ext_sel", 0, Pins("P15"), IOStandard("LVCMOS25")),
     ("ref_clk_src_sel", 0, Pins("J14"), IOStandard("LVCMOS25")),
     ("dac_clk_src_sel", 0, Pins("P16"), IOStandard("LVCMOS25")),
+    ("ref_lo_clk_sel", 0, Pins("L18"), IOStandard("LVCMOS25")),
 
     # DACs
     ("ad9154_rst_n", 0, Pins("U15"), IOStandard("LVCMOS25")),