fhdl/verilog: lower complex slices before reset insertion

m-labs · Jun 30, 2013 · 71b89e4 · 71b89e4
1 parent ded5e56
commit 71b89e4
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
@@ -302,6 +302,7 @@ def convert(f, ios=None, name="top",
 			else:
 				raise KeyError("Unresolved clock domain: '"+cd_name+"'")
 
+	f = lower_complex_slices(f)
 	_insert_resets(f)
 	f = lower_basics(f)
 	fs, lowered_specials = _lower_specials(special_overrides, f.specials)