build/platforms/versaecp55g: add PCIe pins.

m-labs · Nov 9, 2018 · 7303a8a · 7303a8a
1 parent 0c5d42c
commit 7303a8a
Showing 1 changed file with 10 additions and 0 deletions.
diff --git a/migen/build/platforms/versaecp55g.py b/migen/build/platforms/versaecp55g.py
@@ -71,6 +71,16 @@
         Subsignal("n", Pins("A5")),
         IOStandard("LVDS")
     ),
+
+    ("pcie_x1", 0,
+        Subsignal("clk_p", Pins("Y11")),
+        Subsignal("clk_n", Pins("Y12")),
+        Subsignal("rx_p", Pins("Y5")),
+        Subsignal("rx_n", Pins("Y6")),
+        Subsignal("tx_p", Pins("W4")),
+        Subsignal("tx_n", Pins("W5")),
+        Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")),
+    ),
 ]