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migen/fhdl/specials: use fdict to pass memory initialization files to…
… VerilogConvert and print them in __str__ method
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Original file line number | Diff line number | Diff line change |
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@@ -315,6 +315,11 @@ def __str__(self): | |
fdict = OrderedDict() | ||
src, fdict = _printspecials(self.special_overrides, self.f.specials - self.lowered_specials, self.ns, fdict) | ||
r += src | ||
for filename, contents in fdict.items(): | ||
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sbourdeauducq
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f = open(filename, "w") | ||
for data in contents: | ||
f.write("{:x}\n".format(data)) | ||
f.close() | ||
r += "endmodule\n" | ||
return r | ||
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This function should be exported.