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fhdl: RenameClockDomains decorator

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commit 9c7ad6b05bb1343c7448d9207032e2a9e6f6d19a 1 parent cec8fc4
Sébastien Bourdeauducq authored July 26, 2013
13  migen/fhdl/decorators.py
... ...
@@ -1,5 +1,5 @@
1 1
 from migen.fhdl.structure import *
2  
-from migen.fhdl.tools import insert_reset
  2
+from migen.fhdl.tools import insert_reset, rename_clock_domain
3 3
 
4 4
 class ModuleDecorator:
5 5
 	def __init__(self, decorated):
@@ -78,3 +78,14 @@ def __init__(self, *args, **kwargs):
78 78
 	def transform_fragment_insert(self, f, to_insert):
79 79
 		for reset, cdn in to_insert:
80 80
 			f.sync[cdn] = insert_reset(reset, f.sync[cdn])
  81
+
  82
+class RenameClockDomains(ModuleDecorator):
  83
+	def __init__(self, decorated, cd_remapping):
  84
+		ModuleDecorator.__init__(self, decorated)
  85
+		if isinstance(cd_remapping, str):
  86
+			cd_remapping = {"sys": cd_remapping}
  87
+		object.__setattr__(self, "_rc_cd_remapping", cd_remapping)
  88
+
  89
+	def transform_fragment(self, f):
  90
+		for old, new in self._rc_cd_remapping.items():
  91
+			rename_clock_domain(f, old, new)
18  migen/fhdl/module.py
@@ -68,11 +68,11 @@ def __iadd__(self, other):
68 68
 
69 69
 class _ModuleSubmodules(_ModuleProxy):
70 70
 	def __setattr__(self, name, value):
71  
-		self._fm._submodules += [(name, e, dict()) for e in _flat_list(value)]
  71
+		self._fm._submodules += [(name, e) for e in _flat_list(value)]
72 72
 		setattr(self._fm, name, value)
73 73
 	
74 74
 	def __iadd__(self, other):
75  
-		self._fm._submodules += [(None, e, dict()) for e in _flat_list(other)]
  75
+		self._fm._submodules += [(None, e) for e in _flat_list(other)]
76 76
 		return self
77 77
 
78 78
 class _ModuleClockDomains(_ModuleProxy, _ModuleForwardAttr):
@@ -131,20 +131,8 @@ def __setattr__(self, name, value):
131 131
 		else:
132 132
 			object.__setattr__(self, name, value)
133 133
 
134  
-	def add_submodule(self, submodule, cd_remapping=dict(), name=None):
135  
-		if isinstance(cd_remapping, str):
136  
-			cd_remapping = {"sys": cd_remapping}
137  
-		if name is not None:
138  
-			setattr(self, name, submodule)
139  
-		self._submodules.append((name, submodule, cd_remapping))
140  
-
141 134
 	def _collect_submodules(self):
142  
-		r = []
143  
-		for name, submodule, cd_remapping in self._submodules:
144  
-			f = submodule.get_fragment()
145  
-			for old, new in cd_remapping.items():
146  
-				rename_clock_domain(f, old, new)
147  
-			r.append((name, f))
  135
+		r = [(name, submodule.get_fragment()) for name, submodule in self._submodules]
148 136
 		self._submodules = []
149 137
 		return r
150 138
 
2  migen/fhdl/std.py
@@ -2,4 +2,4 @@
2 2
 from migen.fhdl.module import Module
3 3
 from migen.fhdl.specials import TSTriple, Instance, Memory
4 4
 from migen.fhdl.size import log2_int, bits_for, flen
5  
-from migen.fhdl.decorators import DecorateModule, InsertCE, InsertReset
  5
+from migen.fhdl.decorators import DecorateModule, InsertCE, InsertReset, RenameClockDomains
7  migen/genlib/fifo.py
@@ -88,10 +88,9 @@ def __init__(self, width_or_layout, depth):
88 88
 
89 89
 		depth_bits = log2_int(depth, True)
90 90
 
91  
-		produce = GrayCounter(depth_bits+1)
92  
-		self.add_submodule(produce, "write")
93  
-		consume = GrayCounter(depth_bits+1)
94  
-		self.add_submodule(consume, "read")
  91
+		produce = RenameClockDomains(GrayCounter(depth_bits+1), "write")
  92
+		consume = RenameClockDomains(GrayCounter(depth_bits+1), "read")
  93
+		self.submodules += produce, consume
95 94
 		self.comb += [
96 95
 			produce.ce.eq(self.writable & self.we),
97 96
 			consume.ce.eq(self.readable & self.re)

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