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Sebastien Bourdeauducq
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Jan 9, 2012
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from migen.fhdl.structure import * | ||
from migen.fhdl import verilog | ||
from migen.corelogic.fsm import FSM | ||
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s = Signal() | ||
myfsm = FSM('FOO', 'BAR') | ||
myfsm.act(myfsm.FOO, s.eq(1), myfsm.next_state(myfsm.BAR)) | ||
myfsm.act(myfsm.BAR, s.eq(0), myfsm.next_state(myfsm.FOO)) | ||
print(verilog.convert(myfsm.get_fragment(), {s})) |
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from migen.fhdl.structure import * | ||
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class FSM: | ||
def __init__(self, *states): | ||
self._state_bv = BV(bits_for(len(states)-1)) | ||
self._state = Signal(self._state_bv) | ||
self._next_state = Signal(self._state_bv) | ||
for state, n in zip(states, range(len(states))): | ||
setattr(self, state, Constant(n, self._state_bv)) | ||
self.actions = [[] for i in range(len(states))] | ||
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def reset_state(self, state): | ||
self._state.reset = state | ||
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def next_state(self, state): | ||
return self._next_state.eq(state) | ||
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def act(self, state, *statements): | ||
self.actions[state.n] += statements | ||
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def get_fragment(self): | ||
cases = [[Constant(s, self._state_bv)] + a | ||
for s, a in zip(range(len(self.actions)), self.actions) if a] | ||
comb = [ | ||
self._next_state.eq(self._state), | ||
Case(self._state, *cases) | ||
] | ||
sync = [self._state.eq(self._next_state)] | ||
return Fragment(comb, sync) |
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