corelogic -> genlib

examples/basic/complex.py

@@ -1,4 +1,4 @@
-from migen.corelogic.complex import *
+from migen.genlib.complex import *
 from migen.fhdl import verilog
 
 w = Complex(32, 42)

examples/basic/fsm.py

@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
 from migen.fhdl import verilog
-from migen.corelogic.fsm import FSM
+from migen.genlib.fsm import FSM
 
 s = Signal()
 myfsm = FSM("FOO", "BAR")

examples/basic/namer.py

@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
 from migen.fhdl import verilog
-from migen.corelogic.misc import optree
+from migen.genlib.misc import optree
 
 def gen_list(n):
 	s = [Signal() for i in range(n)]

examples/basic/two_dividers.py

@@ -1,5 +1,5 @@
 from migen.fhdl import verilog
-from migen.corelogic import divider
+from migen.genlib import divider
 
 d1 = divider.Divider(16)
 d2 = divider.Divider(16)

examples/basic/using_record.py

@@ -1,5 +1,5 @@
 from migen.fhdl.structure import *
-from migen.corelogic.record import *
+from migen.genlib.record import *
 
 L = [
 	("x", 10, 8),

examples/sim/fir.py

@@ -7,7 +7,7 @@
 
 from migen.fhdl.structure import *
 from migen.fhdl import verilog
-from migen.corelogic.misc import optree
+from migen.genlib.misc import optree
 from migen.fhdl import autofragment
 from migen.sim.generic import Simulator, PureSimulable
 

migen/actorlib/dma_asmi.py

@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
 from migen.flow.actor import *
-from migen.corelogic.buffers import ReorderBuffer
+from migen.genlib.buffers import ReorderBuffer
 
 class SequentialReader(Actor):
 	def __init__(self, port):

migen/actorlib/misc.py

@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
-from migen.corelogic.record import *
-from migen.corelogic.fsm import *
+from migen.genlib.record import *
+from migen.genlib.fsm import *
 from migen.flow.actor import *
 
 # Generates integers from start to maximum-1

migen/bank/eventmanager.py

@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
 from migen.bank.description import *
-from migen.corelogic.misc import optree
+from migen.genlib.misc import optree
 
 class EventSource:
 	def __init__(self):

migen/bus/asmibus.py

@@ -1,5 +1,5 @@
 from migen.fhdl.structure import *
-from migen.corelogic.misc import optree
+from migen.genlib.misc import optree
 from migen.bus.transactions import *
 from migen.sim.generic import Proxy, PureSimulable
 

migen/bus/simple.py

@@ -1,5 +1,5 @@
 from migen.fhdl.structure import *
-from migen.corelogic.misc import optree
+from migen.genlib.misc import optree
 
 (S_TO_M, M_TO_S) = range(2)
 

migen/bus/wishbone.py

@@ -1,7 +1,7 @@
 from migen.fhdl.structure import *
 from migen.fhdl.specials import Memory
-from migen.corelogic import roundrobin
-from migen.corelogic.misc import optree
+from migen.genlib import roundrobin
+from migen.genlib.misc import optree
 from migen.bus.simple import *
 from migen.bus.transactions import *
 from migen.sim.generic import Proxy, PureSimulable

migen/bus/wishbone2asmi.py

@@ -1,9 +1,9 @@
 from migen.fhdl.structure import *
 from migen.fhdl.specials import Memory
 from migen.bus import wishbone
-from migen.corelogic.fsm import FSM
-from migen.corelogic.misc import split, displacer, chooser
-from migen.corelogic.record import Record
+from migen.genlib.fsm import FSM
+from migen.genlib.misc import split, displacer, chooser
+from migen.genlib.record import Record
 
 # cachesize (in 32-bit words) is the size of the data store, must be a power of 2
 class WB2ASMI:

migen/bus/wishbone2csr.py

@@ -1,7 +1,7 @@
 from migen.bus import wishbone
 from migen.bus import csr
 from migen.fhdl.structure import *
-from migen.corelogic.misc import timeline
+from migen.genlib.misc import timeline
 
 class WB2CSR:
 	def __init__(self):

migen/flow/actor.py

@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
-from migen.corelogic.misc import optree
-from migen.corelogic.record import *
+from migen.genlib.misc import optree
+from migen.genlib.record import *
 
 class Endpoint:
 	def __init__(self, token):

migen/flow/network.py

@@ -1,7 +1,7 @@
 from networkx import MultiDiGraph
 
 from migen.fhdl.structure import *
-from migen.corelogic.misc import optree
+from migen.genlib.misc import optree
 from migen.flow.actor import *
 from migen.flow import plumbing
 from migen.flow.isd import DFGReporter

migen/flow/plumbing.py

@@ -1,7 +1,7 @@
 from migen.fhdl.structure import *
 from migen.flow.actor import *
-from migen.corelogic.record import *
-from migen.corelogic.misc import optree
+from migen.genlib.record import *
+from migen.genlib.misc import optree
 
 class Buffer(PipelinedActor):
 	def __init__(self, layout):

migen/pytholite/fsm.py

@@ -1,5 +1,5 @@
 from migen.fhdl import visit as fhdl
-from migen.corelogic.fsm import FSM
+from migen.genlib.fsm import FSM
 
 class AbstractNextState:
 	def __init__(self, target_state):