add indexed part select support

[rroohhh]

This adds support for constant width variable offset slices called indexed part notation in verilog.

[sbourdeauducq]

The more special Verilog features we have, the more complex the code is to test and maintain.
Also, certain cores written would use this indexed part select, whereas others would not. I prefer keeping a single way to do things as much as possible.
This also makes it more complicated to support other backends in the future such as VHDL.
As you indicated on IRC, the benefit of doing this is more readable output. I disagree with this, as having explicit slice boundaries in the generated code makes it easier to spot certain bugs.

Having a part method that returns a _Slice would be OK, on the other hand.

[rroohhh]

The problem with slice is you can't use non constant slice boundaries, here the offset can be dynamic. This can be converted to a shift and a slice, but due to the lowering of complex slices the shift always gets extracted to a assign which sometimes makes it difficult to read imo.

Im not sure how you would convert this into just a slice.

[sbourdeauducq]

That's a good point. Can you add a docstring to part and mention this?
What about signedness and sign extension, did you check that it does the right thing?
Then it seems fine to me.

[rroohhh]

I added a docstring, however I'm not sure how signedness and sign extension would apply here.

[sbourdeauducq]

I'm not sure how signedness and sign extension would apply here

For example, what happens when you add a Part with a signed signal that is smaller than the Part?

[rroohhh]

This does the exact same as a normal part select / _Slice would, it is treated as unsigned by verilog. This is also what is returned by value_bits_sign for a _Part so everything should be correct.

[sbourdeauducq]

Thanks.