VGA: fix the vsync pulses

m-labs · Feb 21, 2012 · 71f9ba5 · 71f9ba5
1 parent 832e989
commit 71f9ba5
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Showing 2 changed files with 12 additions and 12 deletions.
diff --git a/cores/vgafb/rtl/vgafb_ctlif.v b/cores/vgafb/rtl/vgafb_ctlif.v
@@ -88,9 +88,9 @@ always @(posedge sys_clk) begin
 		hscan <= 10'd799;
 
 		vres <= 10'd480;
-		vsync_start <= 10'd491;
-		vsync_end <= 10'd493;
-		vscan <= 10'd523;
+		vsync_start <= 10'd492;
+		vsync_end <= 10'd494;
+		vscan <= 10'd524;
 
 		baseaddress <= {fml_depth{1'b0}};
 

diff --git a/software/libhal/vga.c b/software/libhal/vga.c
@@ -276,9 +276,9 @@ void vga_set_mode(int mode)
 			CSR_VGA_HSYNC_END = 752;
 			CSR_VGA_HSCAN = 799;
 			CSR_VGA_VRES = 480;
-			CSR_VGA_VSYNC_START = 491;
-			CSR_VGA_VSYNC_END = 493;
-			CSR_VGA_VSCAN = 523;
+			CSR_VGA_VSYNC_START = 492;
+			CSR_VGA_VSYNC_END = 494;
+			CSR_VGA_VSCAN = 524;
 			CSR_VGA_CLKSEL = 0;
 			break;
 		case VGA_MODE_800_600: // Pixel clock: 50MHz
@@ -289,9 +289,9 @@ void vga_set_mode(int mode)
 			CSR_VGA_HSYNC_END = 976;
 			CSR_VGA_HSCAN = 1040;
 			CSR_VGA_VRES = 600;
-			CSR_VGA_VSYNC_START = 637;
-			CSR_VGA_VSYNC_END = 643;
-			CSR_VGA_VSCAN = 666;
+			CSR_VGA_VSYNC_START = 636;
+			CSR_VGA_VSYNC_END = 642;
+			CSR_VGA_VSCAN = 665;
 			CSR_VGA_CLKSEL = 1;
 			break;
 		case VGA_MODE_1024_768: // Pixel clock: 65MHz
@@ -302,9 +302,9 @@ void vga_set_mode(int mode)
 			CSR_VGA_HSYNC_END = 1184;
 			CSR_VGA_HSCAN = 1344;
 			CSR_VGA_VRES = 768;
-			CSR_VGA_VSYNC_START = 771;
-			CSR_VGA_VSYNC_END = 777;
-			CSR_VGA_VSCAN = 806;
+			CSR_VGA_VSYNC_START = 772;
+			CSR_VGA_VSYNC_END = 778;
+			CSR_VGA_VSCAN = 807;
 			CSR_VGA_CLKSEL = 2;
 			break;
 	}