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TMU prefetch: assert busy during memory burst in texel fetch unit

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1 parent 09d45f6 commit 7be5065af6f40e5f5f6e7a71e5f897726d5c34f7 @sbourdeauducq sbourdeauducq committed Jul 25, 2011
Showing with 1 addition and 1 deletion.
  1. +1 −1 cores/tmu2/rtl/tmu2_fetchtexel.v
@@ -79,6 +79,6 @@ always @(posedge sys_clk) begin
bcount <= bcount - 2'd1;
end
-assign busy = pipe_stb_o | fml_stb;
+assign busy = pipe_stb_o | fml_stb | fifo_we;
endmodule

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