TMU prefetch: assert busy during memory burst in texel fetch unit

m-labs · Jul 25, 2011 · 7be5065 · 7be5065
1 parent 09d45f6
commit 7be5065
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/cores/tmu2/rtl/tmu2_fetchtexel.v b/cores/tmu2/rtl/tmu2_fetchtexel.v
@@ -79,6 +79,6 @@ always @(posedge sys_clk) begin
 		bcount <= bcount - 2'd1;
 end
 
-assign busy = pipe_stb_o | fml_stb;
+assign busy = pipe_stb_o | fml_stb | fifo_we;
 
 endmodule