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TMU prefetch: true dual port RAM module

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1 parent 8c17500 commit d7b64286d4a1d1a170ee9c5a290a71e3bf510181 @sbourdeauducq sbourdeauducq committed Jul 24, 2011
Showing with 75 additions and 0 deletions.
  1. +75 −0 cores/tmu2/rtl/tmu2_tdpram.v
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+/*
+ * Milkymist SoC
+ * Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Dual-port RAM with dual write-capable port */
+
+module tmu2_tdpram #(
+ parameter depth = 11, /* < log2 of the capacity in words */
+ parameter width = 32
+) (
+ input sys_clk,
+
+ input [depth-1:0] a,
+ input we,
+ input re,
+ input [width-1:0] di,
+ output reg [width-1:0] do,
+
+ input [depth-1:0] a2,
+ input we2,
+ input re2,
+ input [width-1:0] di2,
+ output reg [width-1:0] do2
+);
+
+reg [width-1:0] ram[0:(1 << depth)-1];
+
+
+always @(posedge sys_clk) begin
+ if(we)
+ ram[a] <= di;
+ if(re)
+ do <= ram[a];
+end
+
+always @(posedge sys_clk) begin
+ if(we2)
+ ram[a2] <= di2;
+ if(re2)
+ do2 <= ram[a2];
+end
+
+// synthesis translate_off
+
+/*
+ * For some reason, in Verilog the result of an undefined multiplied by zero
+ * seems to be undefined.
+ * This causes problems with pixels that texcache won't fetch because some fractional
+ * parts are zero: the blend unit yields an undefined result on those, instead of ignoring
+ * the contribution of the undefined pixel.
+ * Work around this by initializing the memories.
+ */
+
+integer i;
+initial begin
+ for(i=0;i<(1 << depth);i=i+1)
+ ram[i] = 0;
+end
+
+// synthesis translate_on
+
+endmodule

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