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spi: register clk output, close #65
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* Changes to the clk_polarity CSR require a SPI transfer to become
  effective.
* The SPI core has a few rough edges and too many corner cases that are
  not handled very elegantly. A rewrite is in the works.
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jordens committed Dec 28, 2017
1 parent eba459e commit 1dc68b0
Showing 1 changed file with 11 additions and 2 deletions.
13 changes: 11 additions & 2 deletions misoc/cores/spi.py
Original file line number Diff line number Diff line change
Expand Up @@ -99,6 +99,7 @@ def __init__(self, data_width, clock_width, bits_width):
self.clk_phase = Signal()
self.start = Signal()
self.cs = Signal()
self.cs_next = Signal()
self.oe = Signal()
self.done = Signal()

Expand Down Expand Up @@ -156,6 +157,8 @@ def __init__(self, data_width, clock_width, bits_width):
self.cg.bias.eq(self.clk_phase),
fsm.ce.eq(self.cg.edge),
self.cs.eq(~fsm.ongoing("IDLE")),
self.cs_next.eq(fsm.before_leaving("IDLE") |
(self.cs & ~fsm.before_entering("IDLE"))),
self.reg.ce.eq(self.cg.edge),
self.bits.ce.eq(self.cg.edge & self.reg.sample),
self.done.eq(self.cg.edge & self.bits.done & fsm.ongoing("HOLD")),
Expand Down Expand Up @@ -304,7 +307,8 @@ def __init__(self, pads, data_width=32, clock_width=8, bits_width=6):

# I/O
all_cs = Signal(len(cs))
self.comb += all_cs.eq((cs & Replicate(spi.cs, len(cs))) ^ ~self._cs_polarity.storage)
self.comb += all_cs.eq((cs & Replicate(spi.cs, len(cs))) ^
~self._cs_polarity.storage)
offset = 0
for pads in pads_list:
cs_n_t = TSTriple(len(pads.cs_n))
Expand All @@ -323,7 +327,12 @@ def __init__(self, pads, data_width=32, clock_width=8, bits_width=6):
self.specials += clk_t.get_tristate(pads.clk)
self.comb += [
clk_t.oe.eq(~self._offline.storage),
clk_t.o.eq((spi.cg.clk & spi.cs) ^ self._clk_polarity.storage),
]
self.sync += [
If(spi.cg.ce & spi.cg.edge,
clk_t.o.eq((~spi.cg.clk & spi.cs_next) ^
self._clk_polarity.storage),
)
]

mosi_t = TSTriple()
Expand Down

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