Convert to new CSR API

cif.py

@@ -45,13 +45,13 @@ def _get_rw_functions(reg_name, reg_base, size):
 
 def get_csr_header(csr_base, bank_array, interrupt_map):
 	r = "#ifndef __HW_CSR_H\n#define __HW_CSR_H\n#include <hw/common.h>\n"
-	for name, rmap in bank_array.banks:
+	for name, csrs, mapaddr, rmap in bank_array.banks:
 		r += "\n/* "+name+" */\n"
-		reg_base = csr_base + 0x800*rmap.address
+		reg_base = csr_base + 0x800*mapaddr
 		r += "#define "+name.upper()+"_BASE "+hex(reg_base)+"\n"
-		for register in rmap.description:
-			nr = (register.get_size() + 7)//8
-			r += _get_rw_functions(name + "_" + register.name, reg_base, nr)
+		for csr in csrs:
+			nr = (csr.size + 7)//8
+			r += _get_rw_functions(name + "_" + csr.name, reg_base, nr)
 			reg_base += 4*nr
 		try:
 			interrupt_nr = interrupt_map[name]

milkymist/asmiprobe/__init__.py

@@ -6,26 +6,24 @@ class ASMIprobe(Module):
 	def __init__(self, hub, trace_depth=16):
 		slots = hub.get_slots()
 		slot_count = len(slots)
-		assert(trace_depth < 256)
-		assert(slot_count < 256)
 
-		self._slot_count = RegisterField(8, READ_ONLY, WRITE_ONLY)
-		self._trace_depth = RegisterField(8, READ_ONLY, WRITE_ONLY)
-		self._slot_status = [RegisterField(2, READ_ONLY, WRITE_ONLY, name="slot_status" + str(i)) for i in range(slot_count)]
-		self._trace = [RegisterField(8, READ_ONLY, WRITE_ONLY, name="trace" + str(i)) for i in range(trace_depth)]
+		self._slot_count = CSRStatus(bits_for(slot_count))
+		self._trace_depth = CSRStatus(bits_for(trace_depth))
+		self._slot_status = [CSRStatus(2, name="slot_status" + str(i)) for i in range(slot_count)]
+		self._trace = [CSRStatus(bits_for(slot_count-1), name="trace" + str(i)) for i in range(trace_depth)]
 
 		###
 
 		self.comb += [
-			self._slot_count.field.w.eq(slot_count),
-			self._trace_depth.field.w.eq(trace_depth)
+			self._slot_count.status.eq(slot_count),
+			self._trace_depth.status.eq(trace_depth)
 		]
 		for slot, status in zip(slots, self._slot_status):
-			self.comb += status.field.w.eq(slot.state)
-		shift_tags = [self._trace[n].field.w.eq(self._trace[n+1].field.w)
+			self.sync += status.status.eq(slot.state)
+		shift_tags = [self._trace[n].status.eq(self._trace[n+1].status)
 			for n in range(len(self._trace) - 1)]
-		shift_tags.append(self._trace[-1].field.w.eq(hub.tag_call))
+		shift_tags.append(self._trace[-1].status.eq(hub.tag_call))
 		self.sync += If(hub.call, *shift_tags)
 
-	def get_registers(self):
+	def get_csrs(self):
 		return [self._slot_count, self._trace_depth] + self._slot_status + self._trace

milkymist/dfii/__init__.py

@@ -3,55 +3,45 @@
 from migen.bus import dfi
 from migen.bank.description import *
 
-class PhaseInjector(Module, AutoReg):
+class PhaseInjector(Module, AutoCSR):
 	def __init__(self, phase):
-		self._cs = Field(1, WRITE_ONLY, READ_ONLY)
-		self._we = Field(1, WRITE_ONLY, READ_ONLY)
-		self._cas = Field(1, WRITE_ONLY, READ_ONLY)
-		self._ras = Field(1, WRITE_ONLY, READ_ONLY)
-		self._wren = Field(1, WRITE_ONLY, READ_ONLY)
-		self._rden = Field(1, WRITE_ONLY, READ_ONLY)
-		self._command = RegisterFields(self._cs, self._we, self._cas, self._ras, self._wren, self._rden)
-		self._command_issue = RegisterRaw()
-
-		self._address = RegisterField(len(phase.address))
-		self._baddress = RegisterField(len(phase.bank))
-
-		self._wrdata = RegisterField(len(phase.wrdata))
-		self._rddata = RegisterField(len(phase.rddata), READ_ONLY, WRITE_ONLY)
+		self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
+		self._command_issue = CSR()
+		self._address = CSRStorage(len(phase.address))
+		self._baddress = CSRStorage(len(phase.bank))
+		self._wrdata = CSRStorage(len(phase.wrdata))
+		self._rddata = CSRStatus(len(phase.rddata))
 
 		###
 
 		self.comb += [
 			If(self._command_issue.re,
-				phase.cs_n.eq(~self._cs.r),
-				phase.we_n.eq(~self._we.r),
-				phase.cas_n.eq(~self._cas.r),
-				phase.ras_n.eq(~self._ras.r)
+				phase.cs_n.eq(~self._command.storage[0]),
+				phase.we_n.eq(~self._command.storage[1]),
+				phase.cas_n.eq(~self._command.storage[2]),
+				phase.ras_n.eq(~self._command.storage[3])
 			).Else(
 				phase.cs_n.eq(1),
 				phase.we_n.eq(1),
 				phase.cas_n.eq(1),
 				phase.ras_n.eq(1)
 			),
-			phase.address.eq(self._address.field.r),
-			phase.bank.eq(self._baddress.field.r),
-			phase.wrdata_en.eq(self._command_issue.re & self._wren.r),
-			phase.rddata_en.eq(self._command_issue.re & self._rden.r),
-			phase.wrdata.eq(self._wrdata.field.r),
+			phase.address.eq(self._address.storage),
+			phase.bank.eq(self._baddress.storage),
+			phase.wrdata_en.eq(self._command_issue.re & self._command.storage[4]),
+			phase.rddata_en.eq(self._command_issue.re & self._command.storage[5]),
+			phase.wrdata.eq(self._wrdata.storage),
 			phase.wrdata_mask.eq(0)
 		]
-		self.sync += If(phase.rddata_valid, self._rddata.field.w.eq(phase.rddata))
+		self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
 
-class DFIInjector(Module, AutoReg):
+class DFIInjector(Module, AutoCSR):
 	def __init__(self, a, ba, d, nphases=1):
 		inti = dfi.Interface(a, ba, d, nphases)
 		self.slave = dfi.Interface(a, ba, d, nphases)
 		self.master = dfi.Interface(a, ba, d, nphases)
 
-		self._sel = Field()
-		self._cke = Field()
-		self._control = RegisterFields(self._sel, self._cke)
+		self._control = CSRStorage(2) # sel, cke
 
 		for n, phase in enumerate(inti.phases):
 			setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
@@ -60,5 +50,5 @@ def __init__(self, a, ba, d, nphases=1):
 
 		connect_inti = dfi.interconnect_stmts(inti, self.master)
 		connect_slave = dfi.interconnect_stmts(self.slave, self.master)
-		self.comb += If(self._sel.r, *connect_slave).Else(*connect_inti)
-		self.comb += [phase.cke.eq(self._cke.r) for phase in inti.phases]
+		self.comb += If(self._control.storage[0], *connect_slave).Else(*connect_inti)
+		self.comb += [phase.cke.eq(self._control.storage[1]) for phase in inti.phases]

milkymist/dvisampler/__init__.py

@@ -10,7 +10,7 @@
 from milkymist.dvisampler.chansync import ChanSync
 from milkymist.dvisampler.resdetection import ResolutionDetection
 
-class DVISampler(Module, AutoReg):
+class DVISampler(Module, AutoCSR):
 	def __init__(self, pads):
 		self.submodules.edid = EDID(pads)
 		self.submodules.clocking = Clocking(pads)

milkymist/dvisampler/chansync.py

@@ -8,12 +8,12 @@
 
 from milkymist.dvisampler.common import channel_layout
 
-class ChanSync(Module, AutoReg):
+class ChanSync(Module, AutoCSR):
 	def __init__(self, nchan=3, depth=8):
 		self.valid_i = Signal()
 		self.chan_synced = Signal()
 
-		self._r_channels_synced = RegisterField(1, READ_ONLY, WRITE_ONLY)
+		self._r_channels_synced = CSRStatus()
 
 		lst_control_starts = []
 		all_control_starts = Signal()
@@ -49,4 +49,4 @@ def __init__(self, nchan=3, depth=8):
 		self.sync.pix += If(~self.valid_i,
 				self.chan_synced.eq(0)
 			).Elif(all_control_starts, self.chan_synced.eq(1))
-		self.specials += MultiReg(self.chan_synced, self._r_channels_synced.field.w)
+		self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status)

milkymist/dvisampler/charsync.py

@@ -6,14 +6,14 @@
 
 from milkymist.dvisampler.common import control_tokens
 
-class CharSync(Module, AutoReg):
+class CharSync(Module, AutoCSR):
 	def __init__(self, required_controls=8):
 		self.raw_data = Signal(10)
 		self.synced = Signal()
 		self.data = Signal(10)
 
-		self._r_char_synced = RegisterField(1, READ_ONLY, WRITE_ONLY)
-		self._r_ctl_pos = RegisterField(bits_for(9), READ_ONLY, WRITE_ONLY)
+		self._r_char_synced = CSRStatus()
+		self._r_ctl_pos = CSRStatus(bits_for(9))
 
 		###
 
@@ -48,7 +48,7 @@ def __init__(self, required_controls=8):
 			),
 			previous_control_position.eq(control_position)
 		]
-		self.specials += MultiReg(self.synced, self._r_char_synced.field.w)
-		self.specials += MultiReg(word_sel, self._r_ctl_pos.field.w)
+		self.specials += MultiReg(self.synced, self._r_char_synced.status)
+		self.specials += MultiReg(word_sel, self._r_ctl_pos.status)
 
 		self.sync.pix += self.data.eq(raw >> word_sel)

milkymist/dvisampler/clocking.py

@@ -4,10 +4,10 @@
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 
-class Clocking(Module, AutoReg):
+class Clocking(Module, AutoCSR):
 	def __init__(self, pads):
-		self._r_pll_reset = RegisterField()
-		self._r_locked = RegisterField(1, READ_ONLY, WRITE_ONLY)
+		self._r_pll_reset = CSRStorage()
+		self._r_locked = CSRStatus()
 
 		self.locked = Signal()
 		self.serdesstrobe = Signal()
@@ -42,7 +42,7 @@ def __init__(self, pads):
 			Instance.Output("LOCKED", pll_locked),
 			Instance.Input("CLKFBIN", clkfbout),
 			Instance.Input("CLKIN", pads.clk),
-			Instance.Input("RST", self._r_pll_reset.field.r)
+			Instance.Input("RST", self._r_pll_reset.storage)
 		)
 
 		locked_async = Signal()
@@ -62,7 +62,7 @@ def __init__(self, pads):
 		self.specials += Instance("BUFG",
 			Instance.Input("I", pll_clk3), Instance.Output("O", self._cd_pix10x.clk))
 		self.specials += MultiReg(locked_async, self.locked, "sys")
-		self.comb += self._r_locked.field.w.eq(self.locked)
+		self.comb += self._r_locked.status.eq(self.locked)
 
 		# sychronize pix+pix5x reset
 		pix_rst_n = 1

milkymist/dvisampler/datacapture.py

@@ -4,16 +4,16 @@
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from migen.bank.description import *
 
-class DataCapture(Module, AutoReg):
+class DataCapture(Module, AutoCSR):
 	def __init__(self, ntbits, invert):
 		self.pad = Signal()
 		self.serdesstrobe = Signal()
 		self.d = Signal(10)
 
-		self._r_dly_ctl = RegisterRaw(4)
-		self._r_dly_busy = RegisterField(1, READ_ONLY, WRITE_ONLY)
-		self._r_phase = RegisterField(2, READ_ONLY, WRITE_ONLY)
-		self._r_phase_reset = RegisterRaw()
+		self._r_dly_ctl = CSR(4)
+		self._r_dly_busy = CSRStatus()
+		self._r_phase = CSRStatus(2)
+		self._r_phase_reset = CSR()
 
 		###
 
@@ -137,11 +137,11 @@ def __init__(self, ntbits, invert):
 			self.do_delay_rst.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[1]),
 			self.do_delay_inc.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[2]),
 			self.do_delay_dec.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[3]),
-			self._r_dly_busy.field.w.eq(sys_delay_pending)
+			self._r_dly_busy.status.eq(sys_delay_pending)
 		]
 
 		# Phase detector control
-		self.specials += MultiReg(Cat(too_late, too_early), self._r_phase.field.w)
+		self.specials += MultiReg(Cat(too_late, too_early), self._r_phase.status)
 		self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix5x")
 		self.comb += [
 			reset_lateness.eq(self.do_reset_lateness.o),

milkymist/dvisampler/edid.py

@@ -4,7 +4,7 @@
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fsm import FSM
 from migen.genlib.misc import chooser
-from migen.bank.description import AutoReg
+from migen.bank.description import AutoCSR
 
 _default_edid = [
 	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
@@ -17,7 +17,7 @@
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF,
 ]
 
-class EDID(Module, AutoReg):
+class EDID(Module, AutoCSR):
 	def __init__(self, pads, default=_default_edid):
 		self.specials.mem = Memory(8, 128, init=default)
 

milkymist/dvisampler/resdetection.py

@@ -3,15 +3,15 @@
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 
-class ResolutionDetection(Module, AutoReg):
+class ResolutionDetection(Module, AutoCSR):
 	def __init__(self, nbits=10):
 		self.hsync = Signal()
 		self.vsync = Signal()
 		self.de = Signal()
 
-		self._hres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
-		self._vres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
-		self._de_cycles = RegisterField(2*nbits, READ_ONLY, WRITE_ONLY)
+		self._hres = CSRStatus(nbits)
+		self._vres = CSRStatus(nbits)
+		self._de_cycles = CSRStatus(2*nbits)
 
 		###
 
@@ -50,8 +50,8 @@ def __init__(self, nbits=10):
 			If(p_hsync & (hcounter != 0), hcounter_st.eq(hcounter)),
 			If(p_vsync & (vcounter != 0), vcounter_st.eq(vcounter))
 		]
-		self.specials += MultiReg(hcounter_st, self._hres.field.w)
-		self.specials += MultiReg(vcounter_st, self._vres.field.w)
+		self.specials += MultiReg(hcounter_st, self._hres.status)
+		self.specials += MultiReg(vcounter_st, self._vres.status)
 
 		# DE
 		de_r = Signal()
@@ -68,4 +68,4 @@ def __init__(self, nbits=10):
 
 		decounter_st = Signal(2*nbits)
 		self.sync.pix += If(pn_de, decounter_st.eq(decounter))
-		self.specials += MultiReg(decounter_st, self._de_cycles.field.w)
+		self.specials += MultiReg(decounter_st, self._de_cycles.status)

milkymist/framebuffer/__init__.py

@@ -220,7 +220,7 @@ def __init__(self, pads, asmiport, simulation=False):
 		g.add_connection(vtg, fifo)
 		self.submodules._comp_actor = CompositeActor(g, debugger=False)
 
-		self._registers = fi.get_registers() + self._comp_actor.get_registers()
+		self._csrs = fi.get_csrs() + self._comp_actor.get_csrs()
 
 		# Drive pads
 		if not simulation:
@@ -233,5 +233,5 @@ def __init__(self, pads, asmiport, simulation=False):
 			]
 		self.comb += pads.psave_n.eq(1)
 
-	def get_registers(self):
-		return self._registers
+	def get_csrs(self):
+		return self._csrs

milkymist/identifier/__init__.py

@@ -15,16 +15,16 @@ def encode_version(version):
 		r |= int(rc)
 	return r
 
-class Identifier(Module, AutoReg):
+class Identifier(Module, AutoCSR):
 	def __init__(self, sysid, version, frequency):
-		self._r_sysid = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
-		self._r_version = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
-		self._r_frequency = RegisterField(32, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+		self._r_sysid = CSRStatus(16)
+		self._r_version = CSRStatus(16)
+		self._r_frequency = CSRStatus(32)
 
 		###
 
 		self.comb += [
-			self._r_sysid.field.w.eq(sysid),
-			self._r_version.field.w.eq(encode_version(version)),
-			self._r_frequency.field.w.eq(frequency)
+			self._r_sysid.status.eq(sysid),
+			self._r_version.status.eq(encode_version(version)),
+			self._r_frequency.status.eq(frequency)
 		]

milkymist/m1crg/__init__.py

@@ -5,7 +5,7 @@
 from migen.fhdl.module import Module
 from migen.bank.description import *
 
-class M1CRG(Module, AutoReg):
+class M1CRG(Module, AutoCSR):
 	def __init__(self, pads, outfreq1x):
 		self.clock_domains.cd_sys = ClockDomain()
 		self.clock_domains.cd_sys2x_270 = ClockDomain()
@@ -18,10 +18,10 @@ def __init__(self, pads, outfreq1x):
 		self.clk4x_wr_strb = Signal()
 		self.clk4x_rd_strb = Signal()
 
-		self._r_cmd_data = RegisterField(10)
-		self._r_send_cmd_data = RegisterRaw()
-		self._r_send_go = RegisterRaw()
-		self._r_status = RegisterField(3, READ_ONLY, WRITE_ONLY)
+		self._r_cmd_data = CSRStorage(10)
+		self._r_send_cmd_data = CSR()
+		self._r_send_go = CSR()
+		self._r_status = CSRStatus(3)
 
 		###
 
@@ -74,7 +74,7 @@ def __init__(self, pads, outfreq1x):
 		self.sync += [
 			If(self._r_send_cmd_data.re,
 				remaining_bits.eq(10),
-				sr.eq(self._r_cmd_data.field.r)
+				sr.eq(self._r_cmd_data.storage)
 			).Elif(transmitting,
 				remaining_bits.eq(remaining_bits - 1),
 				sr.eq(sr[1:])
@@ -95,4 +95,4 @@ def __init__(self, pads, outfreq1x):
 				busy_counter.eq(busy_counter - 1)
 			)
 
-		self.comb += self._r_status.field.w.eq(Cat(busy, vga_progdone, vga_locked))
+		self.comb += self._r_status.status.eq(Cat(busy, vga_progdone, vga_locked))