Initial import

.gitignore

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+__pycache__
+build/*

build.py

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+import os
+import top
+
+# list Verilog sources before changing directory
+verilog_sources = []
+def add_core_dir(d):
+	for root, subFolders, files in os.walk(os.path.join("verilog", d)):
+		for f in files:
+			verilog_sources.append(os.path.join(root, f))
+def add_core_files(d, files):
+	for f in files:
+		verilog_sources.append(os.path.join("verilog", d, f))
+add_core_files("lm32", ["lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
+	"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
+	"lm32_shifter.v", "lm32_multiplier_spartan6.v", "lm32_mc_arithmetic.v",
+	"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
+	"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
+	"jtag_tap_spartan6.v"])
+add_core_dir("uart")
+
+os.system("rm -rf build/*")
+os.chdir("build")
+
+def str2file(filename, contents):
+	f = open(filename, 'w')
+	f.write(contents)
+	f.close()
+
+# generate source
+(src_verilog, src_ucf) = top.Get()
+str2file("soc.v", src_verilog)
+str2file("soc.ucf", src_ucf)
+verilog_sources.append("build/soc.v")
+
+# xst
+xst_prj = ""
+for s in verilog_sources:
+	xst_prj += "verilog work ../" + s + "\n"
+str2file("soc.prj", xst_prj)
+str2file("soc.xst", """run
+-ifn soc.prj
+-top soc
+-ifmt MIXED
+-opt_mode SPEED
+-opt_level 2
+-resource_sharing no
+-reduce_control_sets auto
+-ofn soc.ngc
+-p xc6slx45-fgg484-2""")
+os.system("xst -ifn soc.xst")
+
+# ngdbuild
+os.system("ngdbuild -uc soc.ucf soc.ngc")
+
+# map
+os.system("map -ol high -w soc.ngd")
+
+# par
+os.system("par -ol high -w soc.ncd soc-routed.ncd")
+
+# bitgen
+os.system("bitgen -g LCK_cycle:6 -g Binary:Yes -g INIT_9K:Yes -w soc-routed.ncd soc.bit")

constraints.py

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+def Get(ns, norflash0, uart0):
+	constraints = []
+	def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
+		constraints.append((ns.GetName(signal), vec, pin, iostandard, extra))
+	def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
+		i = 0
+		for p in pins:
+			add(signal, p, i, iostandard, extra)
+			i += 1
+
+	add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
+		"F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
+		"G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19"],
+		extra="SLEW = FAST | DRIVE = 8")
+	add_vec(norflash0.d, ["AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7",
+		"AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"],
+		extra = "SLEW = FAST | DRIVE = 8 | PULLDOWN")
+	add(norflash0.oe_n, "M22", extra="SLEW = FAST | DRIVE = 8")
+	add(norflash0.we_n, "N20", extra="SLEW = FAST | DRIVE = 8")
+	add(norflash0.ce_n, "M21", extra="SLEW = FAST | DRIVE = 8")
+	add(norflash0.rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
+
+	add(uart0.tx, "L17", extra="SLEW = SLOW")
+	add(uart0.rx, "K18", extra="PULLUP")
+
+	r = ""
+	for c in constraints:
+		r += "NET \"" + c[0]
+		if c[1] >= 0:
+			r += "(" + str(c[1]) + ")"
+		r += "\" LOC = " + c[2] 
+		r += " | IOSTANDARD = " + c[3]
+		if c[4]:
+			r += " | " + c[4]
+		r += ";\n"
+
+	r += """
+NET "sys_clk" LOC = AB11 | IOSTANDARD = LVCMOS33;
+NET "sys_clk" TNM_NET = "GRPclk50";
+TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
+
+NET "sys_rst" LOC = AA4 | IOSTANDARD = LVCMOS33;
+	"""
+
+	return r

milkymist/lm32/__init__.py

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+from migen.fhdl import structure as f
+from migen.bus import wishbone
+
+class Inst:
+	def __init__(self):
+		self.ibus = i = wishbone.Master("lm32i")
+		self.dbus = d = wishbone.Master("lm32d")
+		f.Declare(self, "interrupt", f.BV(32))
+		f.Declare(self, "ext_break")
+		self._inst = f.Instance("lm32_top",
+			[("I_ADR_O", i.adr_o),
+			("I_DAT_O", i.dat_o),
+			("I_SEL_O", i.sel_o),
+			("I_CYC_O", i.cyc_o),
+			("I_STB_O", i.stb_o),
+			("I_WE_O", i.we_o),
+			("I_CTI_O", i.cti_o),
+			("I_LOCK_O", f.BV(1)),
+			("I_BTE_O", i.bte_o),
+			("D_ADR_O", d.adr_o),
+			("D_DAT_O", d.dat_o),
+			("D_SEL_O", d.sel_o),
+			("D_CYC_O", d.cyc_o),
+			("D_STB_O", d.stb_o),
+			("D_WE_O", d.we_o),
+			("D_CTI_O", d.cti_o),
+			("D_LOCK_O", f.BV(1)),
+			("D_BTE_O", d.bte_o)],
+			[("interrupt", self.interrupt),
+			#("ext_break", self.ext_break),
+			("I_DAT_I", i.dat_i),
+			("I_ACK_I", i.ack_i),
+			("I_ERR_I", i.err_i),
+			("I_RTY_I", f.BV(1)),
+			("D_DAT_I", d.dat_i),
+			("D_ACK_I", d.ack_i),
+			("D_ERR_I", d.err_i),
+			("D_RTY_I", f.BV(1))],
+			[],
+			"clk_i",
+			"rst_i",
+			"lm32")
+
+	def GetFragment(self):
+		comb = [
+			f.Assign(self._inst.ins["I_RTY_I"], 0),
+			f.Assign(self._inst.ins["D_RTY_I"], 0)
+		]
+		return f.Fragment(comb=comb, instances=[self._inst])

milkymist/norflash/__init__.py

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+from migen.fhdl import structure as f
+from migen.bus import wishbone
+from migen.corelogic import timeline
+from functools import partial
+
+class Inst:
+	def __init__(self, adr_width, rd_timing):
+		self.bus = wishbone.Slave("norflash")
+		d = partial(f.Declare, self)
+		d("adr", f.BV(adr_width-1))
+		d("d", f.BV(16))
+		d("oe_n")
+		d("we_n")
+		d("ce_n")
+		d("rst_n")
+		self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i,
+			[(0, [f.Assign(self.adr, f.Cat(0, self.bus.adr_i[2:adr_width]))]),
+			(rd_timing, [
+				f.Assign(self.bus.dat_o[16:], self.d),
+				f.Assign(self.adr, f.Cat(1, self.bus.adr_i[2:adr_width]))]),
+			(2*rd_timing, [
+				f.Assign(self.bus.dat_o[:16], self.d),
+				f.Assign(self.bus.ack_o, 1)]),
+			(2*rd_timing+1, [
+				f.Assign(self.bus.ack_o, 0)])])
+
+	def GetFragment(self):
+		comb = [f.Assign(self.oe_n, 0), f.Assign(self.we_n, 1),
+			f.Assign(self.ce_n, 0), f.Assign(self.rst_n, 1)]
+		return f.Fragment(comb, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n, self.rst_n}) \
+			+ self.timeline.GetFragment()

milkymist/uart/__init__.py

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+from migen.fhdl import structure as f
+from migen.bus import csr
+
+class Inst:
+	def __init__(self, csr_addr, clk_freq, baud=115200, break_en_default=f.Constant(0)):
+		self.bus = csr.Slave("uart")
+		f.Declare(self, "tx")
+		f.Declare(self, "rx")
+		f.Declare(self, "irq")
+		f.Declare(self, "brk")
+		self._inst = f.Instance("uart",
+			[("csr_do", self.bus.d_o),
+			("uart_tx", self.tx),
+			("irq", self.irq),
+			("break", self.brk)],
+			[("csr_a", self.bus.a_i),
+			("csr_we", self.bus.we_i),
+			("csr_di", self.bus.d_i),
+			("uart_rx", self.rx)],
+			[("csr_addr", f.Constant(csr_addr, f.BV(4))),
+			("clk_freq", clk_freq),
+			("baud", baud),
+			("break_en_default", break_en_default)],
+			"sys_clk",
+			"sys_rst")
+
+	def GetFragment(self):
+		return f.Fragment(instances=[self._inst], pads={self.tx, self.rx})

tb/norflash/Makefile

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+SOURCES=tb_norflash.v norflash.v
+
+all: tb_norflash
+
+isim: tb_norflash
+	./tb_norflash
+
+cversim: $(SOURCES)
+	cver $(SOURCES)
+
+norflash.v: norflash_conv.py
+	python3 norflash_conv.py > norflash.v
+
+clean:
+	rm -f tb_norflash verilog.log norflash.vcd norflash.v
+
+tb_norflash: $(SOURCES)
+	iverilog -o tb_norflash $(SOURCES)
+
+.PHONY: clean sim cversim

tb/norflash/norflash_conv.py

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+from migen.fhdl import verilog
+from migen.fhdl import structure as f
+from migen.bus import wishbone
+from milkymist import norflash
+
+norflash0 = norflash.Inst(25, 12)
+frag = norflash0.GetFragment()
+v = verilog.Convert(frag, name="norflash",
+	ios={norflash0.bus.cyc_i, norflash0.bus.stb_i, norflash0.bus.we_i, norflash0.bus.adr_i, norflash0.bus.sel_i, norflash0.bus.dat_i, norflash0.bus.dat_o, norflash0.bus.ack_o})
+print(v)

tb/norflash/tb_norflash.v

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+/*
+ * Milkymist SoC
+ * Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+`timescale 1ns / 1ps
+
+module tb_norflash();
+
+reg sys_clk;
+reg sys_rst;
+
+reg [31:0] wb_adr_i;
+wire [31:0] wb_dat_o;
+reg wb_cyc_i;
+reg wb_stb_i;
+wire wb_ack_o;
+reg [3:0] wb_sel_i;
+
+wire [23:0] flash_adr;
+wire [15:0] flash_d;
+reg [15:0] flash_do;
+
+always @(flash_adr) #110 flash_do <= flash_adr[15:0] + 16'b1;
+
+norflash dut(
+	.sys_clk(sys_clk),
+	.sys_rst(sys_rst),
+
+	.wishbone_norflash_adr_i(wb_adr_i),
+	.wishbone_norflash_dat_o(wb_dat_o),
+	.wishbone_norflash_cyc_i(wb_cyc_i),
+	.wishbone_norflash_stb_i(wb_stb_i),
+	.wishbone_norflash_ack_o(wb_ack_o),
+	.wishbone_norflash_sel_i(wb_sel_i),
+
+	.norflash_adr(flash_adr),
+	.norflash_d(flash_d),
+	.norflash_oe_n(flash_oe_n),
+	.norflash_we_n(flash_we_n)
+);
+
+//assign flash_d = flash_oe_n ? 16'bz : flash_do;
+assign flash_d = flash_do;
+
+task wbread;
+	input [31:0] address;
+	integer i;
+	begin
+		wb_adr_i <= address;
+		wb_cyc_i <= 1'b1;
+		wb_stb_i <= 1'b1;
+
+		i = 1;
+		while(~wb_ack_o) begin
+			#5 sys_clk <= 1'b1;
+			#5 sys_clk <= 1'b0;
+			i = i + 1;
+		end
+
+		$display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
+
+		wb_cyc_i <= 1'b0;
+		wb_stb_i <= 1'b0;
+
+		/* Let the core release its ack */
+		#5 sys_clk <= 1'b1;
+		#5 sys_clk <= 1'b0;
+	end
+endtask
+
+initial begin
+	$dumpfile("norflash.vcd");
+	$dumpvars(1, dut);
+
+	sys_rst <= 1'b1;
+	sys_clk <= 1'b0;
+
+	wb_adr_i <= 32'h00000000;
+	wb_cyc_i <= 1'b0;
+	wb_stb_i <= 1'b0;
+	wb_sel_i <= 4'b1111;
+
+	#5 sys_clk <= 1'b1;
+	#5 sys_clk <= 1'b0;
+
+	sys_rst <= 1'b0;
+	#5 sys_clk <= 1'b1;
+	#5 sys_clk <= 1'b0;
+
+	wbread(32'h00000000);
+	wbread(32'h00000004);
+
+	wb_sel_i = 4'b0010;
+	wbread(32'h0000fff1);
+
+	wb_sel_i = 4'b0100;
+	wbread(32'h0000fff2);
+
+	wb_sel_i = 4'b1000;
+	wbread(32'h0000fff3);
+
+	wb_sel_i = 4'b0100;
+	wbread(32'h0000fff0);
+
+	wb_sel_i = 4'b1111;
+	wbread(32'h00000010);
+	#5 sys_clk = 1'b1;
+	#5 sys_clk = 1'b0;
+	#5 sys_clk = 1'b1;
+	#5 sys_clk = 1'b0;
+	wbread(32'h00000040);
+
+	$finish;
+end
+
+endmodule