sayma: LOC clock buffers involved in SDRAM clocking

Those positions are what is obtained without SAWG (when the SDRAM is more reliable).

misoc/targets/sayma_amc.py

@@ -47,9 +47,11 @@ def __init__(self, platform):
                 p_CLKOUT1_DIVIDE=5, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_clk200,
             ),
             Instance("BUFGCE_DIV", name="main_bufgce_div",
+                attr={("LOC", "BUFGCE_DIV_X1Y0")},
                 p_BUFGCE_DIVIDE=4,
                 i_CE=1, i_I=pll_sys4x, o_O=self.cd_sys.clk),
             Instance("BUFGCE", name="main_bufgce",
+                attr={("LOC", "BUFGCE_X1Y14")},
                 i_CE=1, i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
             Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
             AsyncResetSynchronizer(self.cd_clk200, ~pll_locked),