s6ddrphy: fix read latency

m-labs · Jun 11, 2013 · ce2f088 · ce2f088
1 parent 4d0c80c
commit ce2f088
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/top.py b/top.py
@@ -44,7 +44,7 @@ def ns(t, margin=True):
 	tRFC=ns(70),
 
 	CL=3,
-	read_latency=4,
+	read_latency=5,
 	write_latency=0,
 
 	read_time=32,

diff --git a/verilog/s6ddrphy/s6ddrphy.v b/verilog/s6ddrphy/s6ddrphy.v
@@ -7,7 +7,7 @@
  *
  * Assert dfi_rddata_en in the same cycle as the read
  * command. The data will come back on dfi_rddata
- * 4 cycles later, along with the assertion of
+ * 5 cycles later, along with the assertion of
  * dfi_rddata_valid.
  *
  * This PHY only supports CAS Latency 3.