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s6ddrphy: fix read latency

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commit ce2f08844a8e93e684d1e6fe7dad537b08723258 1 parent 4d0c80c
Sébastien Bourdeauducq sbourdeauducq authored
Showing with 2 additions and 2 deletions.
  1. +1 −1  top.py
  2. +1 −1  verilog/s6ddrphy/s6ddrphy.v
2  top.py
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@@ -44,7 +44,7 @@ def ns(t, margin=True):
tRFC=ns(70),
CL=3,
- read_latency=4,
+ read_latency=5,
write_latency=0,
read_time=32,
2  verilog/s6ddrphy/s6ddrphy.v
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@@ -7,7 +7,7 @@
*
* Assert dfi_rddata_en in the same cycle as the read
* command. The data will come back on dfi_rddata
- * 4 cycles later, along with the assertion of
+ * 5 cycles later, along with the assertion of
* dfi_rddata_valid.
*
* This PHY only supports CAS Latency 3.
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