liteeth_mini: fix imports, replace Counter and FlipFlop

misoc/cores/liteeth_mini/common.py

@@ -2,13 +2,7 @@
 from migen.genlib.record import *
 
 from misoc.interconnect.csr import *
-
-
-# TODO: rewrite without dataflow or implement those
-# from migen.flow.actor import *
-# from migen.actorlib.structuring import Converter, Pipeline
-# from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
-# from migen.actorlib.packet import *
+from misoc.interconnect.stream import *
 
 
 class Port:

misoc/cores/liteeth_mini/mac/core/__init__.py

@@ -19,8 +19,8 @@ def __init__(self, phy, dw, endianness="big",
         # Interpacket gap
         tx_gap_inserter = gap.LiteEthMACGap(phy.dw)
         rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True)
-        self.submodules += RenameClockDomains(tx_gap_inserter, "eth_tx")
-        self.submodules += RenameClockDomains(rx_gap_checker, "eth_rx")
+        self.submodules += ClockDomainsRenamer("eth_tx")(tx_gap_inserter)
+        self.submodules += ClockDomainsRenamer("eth_rx")(rx_gap_checker)
 
         tx_pipeline += [tx_gap_inserter]
         rx_pipeline += [rx_gap_checker]
@@ -31,14 +31,14 @@ def __init__(self, phy, dw, endianness="big",
             # Preamble insert/check
             preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
             preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
-            self.submodules += RenameClockDomains(preamble_inserter, "eth_tx")
-            self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
+            self.submodules += ClockDomainsRenamer("eth_tx")(preamble_inserter)
+            self.submodules += ClockDomainsRenamer("eth_rx")(preamble_checker)
 
             # CRC insert/check
             crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw))
             crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw))
-            self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
-            self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
+            self.submodules += ClockDomainsRenamer("eth_tx")(crc32_inserter)
+            self.submodules += ClockDomainsRenamer("eth_rx")(crc32_checker)
 
             tx_pipeline += [preamble_inserter, crc32_inserter]
             rx_pipeline += [preamble_checker, crc32_checker]
@@ -47,8 +47,8 @@ def __init__(self, phy, dw, endianness="big",
         if with_padding:
             padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60)
             padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60)
-            self.submodules += RenameClockDomains(padding_inserter, "eth_tx")
-            self.submodules += RenameClockDomains(padding_checker, "eth_rx")
+            self.submodules += ClockDomainsRenamer("eth_tx")(padding_inserter)
+            self.submodules += ClockDomainsRenamer("eth_rx")(padding_checker)
 
             tx_pipeline += [padding_inserter]
             rx_pipeline += [padding_checker]
@@ -57,8 +57,8 @@ def __init__(self, phy, dw, endianness="big",
         if dw != 8:
             tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw)
             rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw)
-            self.submodules += RenameClockDomains(tx_last_be, "eth_tx")
-            self.submodules += RenameClockDomains(rx_last_be, "eth_rx")
+            self.submodules += ClockDomainsRenamer("eth_tx")(tx_last_be)
+            self.submodules += ClockDomainsRenamer("eth_rx")(rx_last_be)
 
             tx_pipeline += [tx_last_be]
             rx_pipeline += [rx_last_be]
@@ -72,8 +72,8 @@ def __init__(self, phy, dw, endianness="big",
             rx_converter = Converter(eth_phy_description(phy.dw),
                                      eth_phy_description(dw),
                                      reverse=reverse)
-            self.submodules += RenameClockDomains(tx_converter, "eth_tx")
-            self.submodules += RenameClockDomains(rx_converter, "eth_rx")
+            self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter)
+            self.submodules += ClockDomainsRenamer("eth_rx")(rx_converter)
 
             tx_pipeline += [tx_converter]
             rx_pipeline += [rx_converter]
@@ -85,14 +85,16 @@ def __init__(self, phy, dw, endianness="big",
             fifo_depth = 64
         tx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
         rx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
-        self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
-        self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
+        self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc)
+        self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc)
 
         tx_pipeline += [tx_cdc]
         rx_pipeline += [rx_cdc]
 
-        # Graph
-        self.submodules.tx_pipeline = Pipeline(*reversed(tx_pipeline))
-        self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
-
-        self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source
+        tx_pipeline_r = list(reversed(tx_pipeline))
+        for s, d in zip(tx_pipeline_r, tx_pipeline_r[1:]):
+            self.comb += s.source.connect(d.sink)
+        for s, d in zip(rx_pipeline, rx_pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        self.sink = tx_pipeline[-1].sink
+        self.source = rx_pipeline[-1].source

misoc/cores/liteeth_mini/mac/core/crc.py

@@ -1,4 +1,11 @@
+from collections import OrderedDict
+from functools import reduce
+from operator import xor
+
 from migen import *
+from migen.genlib.misc import chooser
+
+from misoc.interconnect.stream import *
 
 
 class LiteEthMACCRCEngine(Module):
@@ -67,7 +74,7 @@ def _optimize_eq(l):
                     xors += [self.last[n]]
                 elif t == "din":
                     xors += [self.data[n]]
-            self.comb += self.next[i].eq(optree("^", xors))
+            self.comb += self.next[i].eq(reduce(xor, xors))
 
 
 @ResetInserter()
@@ -224,7 +231,7 @@ def __init__(self, crc_class, description):
         self.submodules += crc
         ratio = crc.width//dw
 
-        fifo = InsertReset(SyncFIFO(description, ratio + 1))
+        fifo = ResetInserter()(SyncFIFO(description, ratio + 1))
         self.submodules += fifo
 
         fsm = FSM(reset_state="RESET")

misoc/cores/liteeth_mini/mac/core/gap.py

@@ -3,7 +3,8 @@
 from migen import *
 from migen.genlib.fsm import *
 
-from misoc.cores.liteeth_mini.common import eth_phy_description
+from misoc.interconnect.stream import Sink, Source
+from misoc.cores.liteeth_mini.common import eth_phy_description, eth_interpacket_gap
 
 
 class LiteEthMACGap(Module):
@@ -14,20 +15,28 @@ def __init__(self, dw, ack_on_gap=False):
         # # #
 
         gap = math.ceil(eth_interpacket_gap/(dw//8))
-        self.submodules.counter = counter = Counter(max=gap)
+        counter = Signal(max=gap)
+        counter_reset = Signal()
+        counter_ce = Signal()
+        self.sync += \
+            If(counter_reset,
+               counter.eq(0)
+            ).Elif(counter_ce,
+                counter.eq(counter + 1)
+            )
 
         self.submodules.fsm = fsm = FSM(reset_state="COPY")
         fsm.act("COPY",
-            counter.reset.eq(1),
+            counter_reset.eq(1),
             Record.connect(sink, source),
             If(sink.stb & sink.eop & sink.ack,
                 NextState("GAP")
             )
         )
         fsm.act("GAP",
-            counter.ce.eq(1),
+            counter_ce.eq(1),
             sink.ack.eq(int(ack_on_gap)),
-            If(counter.value == (gap-1),
+            If(counter == (gap-1),
                 NextState("COPY")
             )
         )

misoc/cores/liteeth_mini/mac/core/last_be.py

@@ -1,5 +1,6 @@
 from migen import *
 
+from misoc.interconnect.stream import *
 from misoc.cores.liteeth_mini.common import eth_phy_description
 
 

misoc/cores/liteeth_mini/mac/core/padding.py

@@ -1,9 +1,10 @@
+import math
+
 from migen import *
 
+from misoc.interconnect.stream import *
 from misoc.cores.liteeth_mini.common import eth_phy_description
 
-# TODO: rewrite without Counter
-
 
 class LiteEthMACPaddingInserter(Module):
     def __init__(self, dw, padding):
@@ -14,19 +15,26 @@ def __init__(self, dw, padding):
 
         padding_limit = math.ceil(padding/(dw/8))-1
 
-        self.submodules.counter = counter = Counter(16, reset=1)
+        counter = Signal(16, reset=1)
         counter_done = Signal()
+        counter_reset = Signal()
+        counter_ce = Signal()
+        self.sync += If(counter_reset,
+                            counter.eq(1)
+                        ).Elif(counter_ce,
+                            counter.eq(counter + 1)
+                        )
         self.comb += [
-            counter.reset.eq(sink.stb & sink.sop & sink.ack),
-            counter.ce.eq(source.stb & source.ack),
-            counter_done.eq(counter.value >= padding_limit),
+            counter_reset.eq(sink.stb & sink.sop & sink.ack),
+            counter_ce.eq(source.stb & source.ack),
+            counter_done.eq(counter >= padding_limit),
         ]
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
             Record.connect(sink, source),
             If(source.stb & source.ack,
-                counter.ce.eq(1),
+                counter_ce.eq(1),
                 If(sink.eop,
                     If(~counter_done,
                         source.eop.eq(0),
@@ -54,7 +62,7 @@ def __init__(self, dw, packet_min_length):
 
         # # #
 
-        # XXX see if we should drop the packet when
+        # TODO: see if we should drop the packet when
         # payload size < minimum ethernet payload size
         self.comb += Record.connect(sink, source)
 

misoc/cores/liteeth_mini/mac/core/preamble.py

@@ -1,7 +1,9 @@
 from migen import *
 from migen.genlib.fsm import *
+from migen.genlib.misc import chooser
 from migen.genlib.record import Record
 
+from misoc.interconnect.stream import *
 from misoc.cores.liteeth_mini.common import eth_phy_description, eth_preamble
 
 

misoc/cores/liteeth_mini/mac/frontend/sram.py

@@ -2,6 +2,7 @@
 
 from misoc.interconnect.csr import *
 from misoc.interconnect.csr_eventmanager import *
+from misoc.interconnect.stream import *
 
 from misoc.cores.liteeth_mini.common import eth_phy_description
 
@@ -38,12 +39,19 @@ def __init__(self, dw, depth, nslots=2):
             ).Else(
                 increment.eq(4)
             )
-        counter = Counter(lengthbits, increment=increment)
-        self.submodules += counter
+        counter = Signal(lengthbits)
+        counter_reset = Signal()
+        counter_ce = Signal()
+        self.sync += If(counter_reset,
+                        counter.eq(0)
+                    ).Elif(counter_ce,
+                        counter.eq(counter + increment)
+                    )
 
         # slot computation
-        slot = Counter(slotbits)
-        self.submodules += slot
+        slot = Signal(slotbits)
+        slot_ce = Signal()
+        self.sync += If(slot_ce, slot.eq(slot + 1))
 
         ongoing = Signal()
 
@@ -59,13 +67,13 @@ def __init__(self, dw, depth, nslots=2):
             If(sink.stb & sink.sop,
                 If(fifo.sink.ack,
                     ongoing.eq(1),
-                    counter.ce.eq(1),
+                    counter_ce.eq(1),
                     NextState("WRITE")
                 )
             )
         )
         fsm.act("WRITE",
-            counter.ce.eq(sink.stb),
+            counter_ce.eq(sink.stb),
             ongoing.eq(1),
             If(sink.stb & sink.eop,
                 If((sink.error & sink.last_be) != 0,
@@ -76,16 +84,16 @@ def __init__(self, dw, depth, nslots=2):
             )
         )
         fsm.act("DISCARD",
-            counter.reset.eq(1),
+            counter_reset.eq(1),
             NextState("IDLE")
         )
         self.comb += [
-            fifo.sink.slot.eq(slot.value),
-            fifo.sink.length.eq(counter.value)
+            fifo.sink.slot.eq(slot),
+            fifo.sink.length.eq(counter)
         ]
         fsm.act("TERMINATE",
-            counter.reset.eq(1),
-            slot.ce.eq(1),
+            counter_reset.eq(1),
+            slot_ce.eq(1),
             fifo.sink.stb.eq(1),
             NextState("IDLE")
         )
@@ -108,13 +116,13 @@ def __init__(self, dw, depth, nslots=2):
         cases = {}
         for n, port in enumerate(ports):
             cases[n] = [
-                ports[n].adr.eq(counter.value[2:]),
+                ports[n].adr.eq(counter[2:]),
                 ports[n].dat_w.eq(sink.data),
                 If(sink.stb & ongoing,
                     ports[n].we.eq(0xf)
                 )
             ]
-        self.comb += Case(slot.value, cases)
+        self.comb += Case(slot, cases)
 
 
 class LiteEthMACSRAMReader(Module, AutoCSR):
@@ -147,7 +155,15 @@ def __init__(self, dw, depth, nslots=2):
         ]
 
         # length computation
-        self.submodules.counter = counter = Counter(lengthbits, increment=4)
+        counter = Signal(lengthbits)
+        counter_reset = Signal()
+        counter_ce = Signal()
+        self.sync += If(counter_reset,
+                            counter.eq(0)
+                        ).Elif(counter_ce,
+                            counter.eq(counter + 4)
+                        )
+
 
         # fsm
         first = Signal()
@@ -158,7 +174,7 @@ def __init__(self, dw, depth, nslots=2):
         self.submodules += fsm
 
         fsm.act("IDLE",
-            counter.reset.eq(1),
+            counter_reset.eq(1),
             If(fifo.source.stb,
                 NextState("CHECK")
             )
@@ -189,7 +205,7 @@ def __init__(self, dw, depth, nslots=2):
             source.sop.eq(first),
             source.eop.eq(last),
             If(source.ack,
-                counter.ce.eq(~last),
+                counter_ce.eq(~last),
                 NextState("CHECK")
             )
         )
@@ -207,7 +223,7 @@ def __init__(self, dw, depth, nslots=2):
                 first.eq(0)
             )
         ]
-        self.comb += last.eq((counter.value + 4) >= fifo.source.length)
+        self.comb += last.eq((counter + 4) >= fifo.source.length)
         self.sync += last_d.eq(last)
 
         # memory
@@ -223,7 +239,7 @@ def __init__(self, dw, depth, nslots=2):
 
         cases = {}
         for n, port in enumerate(ports):
-            self.comb += ports[n].adr.eq(counter.value[2:])
+            self.comb += ports[n].adr.eq(counter[2:])
             cases[n] = [source.data.eq(port.dat_r)]
         self.comb += Case(rd_slot, cases)
 

misoc/cores/liteeth_mini/mac/frontend/wishbone.py

@@ -1,10 +1,11 @@
 from migen import *
 from migen.fhdl.simplify import FullMemoryWE
 
-from misoc.cores.liteeth_mini.common import eth_phy_description
-from misoc.cores.liteeth_mini.mac.frontend import sram
 from misoc.interconnect import wishbone
 from misoc.interconnect.csr import *
+from misoc.interconnect.stream import *
+from misoc.cores.liteeth_mini.common import eth_phy_description, buffer_depth
+from misoc.cores.liteeth_mini.mac.frontend import sram
 
 
 class LiteEthMACWishboneInterface(Module, AutoCSR):