- RX now enters DONE state 1 clock earlier to avoid delay
- RX now checks for one more bit (taking (divisor+1)-long time span) while making the received data ready for collection

* `TX.continuous` is an externally driven Signal, resets to 0 (deasserted)
  * When asserted, TX assumes that `TX.data` is valid AT THE SAME TIME when the start bit starts to be sent out
  * When deasserted, TX assumes that `TX.data` is valid BEFORE the start bit is sent, and AT THE SAME TIME when `TX.ack` is asserted

* This FV case now inserts any delay (0 - divisor+1) between the final bit and the start bit (0) of the next sequence.