vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly.

Do this to make sure all buffers, tristate/differential or not, are
instantiated the exact same way, and are subject to the same set of
toolchain bugs, if any.

nmigen/vendor/xilinx_7series.py

@@ -234,15 +234,23 @@ def get_input(self, pin, port, attrs, invert):
                             valid_xdrs=(0, 1, 2), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
-        m.d.comb += i.eq(port)
+        for bit in range(len(port)):
+            m.submodules += Instance("IBUF",
+                i_I=port[bit],
+                o_O=i[bit]
+            )
         return m
 
     def get_output(self, pin, port, attrs, invert):
         self._check_feature("single-ended output", pin, attrs,
                             valid_xdrs=(0, 1, 2), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
-        m.d.comb += port.eq(o)
+        for bit in range(len(port)):
+            m.submodules += Instance("OBUF",
+                i_I=o[bit],
+                o_O=port[bit]
+            )
         return m
 
     def get_tristate(self, pin, port, attrs, invert):

nmigen/vendor/xilinx_spartan6.py

@@ -249,15 +249,23 @@ def get_input(self, pin, port, attrs, invert):
                             valid_xdrs=(0, 1, 2), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
-        m.d.comb += i.eq(port)
+        for bit in range(len(port)):
+            m.submodules += Instance("IBUF",
+                i_I=port[bit],
+                o_O=i[bit]
+            )
         return m
 
     def get_output(self, pin, port, attrs, invert):
         self._check_feature("single-ended output", pin, attrs,
                             valid_xdrs=(0, 1, 2), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
-        m.d.comb += port.eq(o)
+        for bit in range(len(port)):
+            m.submodules += Instance("OBUF",
+                i_I=o[bit],
+                o_O=port[bit]
+            )
         return m
 
     def get_tristate(self, pin, port, attrs, invert):