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back.rtlil: use one $meminit cell, not one per word.
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This is *far* more efficient.
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whitequark committed Dec 24, 2018
1 parent 98f554a commit d47c1f8
Showing 1 changed file with 12 additions and 10 deletions.
22 changes: 12 additions & 10 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
Expand Up @@ -644,21 +644,23 @@ def convert_fragment(builder, fragment, name, top):
memories[memory] = module.memory(width=memory.width, size=memory.depth,
name=memory.name)
addr_bits = bits_for(memory.depth)
data_parts = ["{}'".format(memory.width * memory.depth)]
for addr in range(memory.depth):
if addr < len(memory.init):
data = memory.init[addr]
else:
data = 0
module.cell("$meminit", ports={
"\\ADDR": rhs_compiler(ast.Const(addr, addr_bits)),
"\\DATA": rhs_compiler(ast.Const(data, memory.width)),
}, params={
"MEMID": memories[memory],
"ABITS": addr_bits,
"WIDTH": memory.width,
"WORDS": 1,
"PRIORITY": 0,
})
data_parts.append("{:0{}b}".format(data, memory.width))
module.cell("$meminit", ports={
"\\ADDR": rhs_compiler(ast.Const(0, addr_bits)),
"\\DATA": "".join(data_parts),
}, params={
"MEMID": memories[memory],
"ABITS": addr_bits,
"WIDTH": memory.width,
"WORDS": memory.depth,
"PRIORITY": 0,
})

param_value = memories[memory]

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