I2C

[trejan]

I suspect P3+P4 are I2C and used to communicate with the RP2040 seen on the prototype M.2 HAT. The BCM2712 has two pins muxed to the I2C peripheral and they're named PCIE_SCL/SDA. It isn't the RP1 either as that has a separate I2C bus.

These two pins are configured with the weak internal pulldown enabled and always read as low. The M.2 HAT presumably has the missing I2C pullup resistors.

114: a1    pd | lo // PCIE_SDA/GPIO14 = SPI_S_MOSI_OR_BSC_S_SDA
115: a1    pd | lo // PCIE_SCL/GPIO15 = SPI_S_SCK_OR_BSC_S_SCL

Should be easy enough to confirm by running pinctrl before & after pulling the pins high.

[m1geo]

Thanks for this. I'll add provision for this on the board. That's really useful knowledge. I'm also pretty sure that P1 is RST and P2 is CLKREQ (based on probing around with the scope some more). Means there is likely no presence detect (or some magic the RP2040 is doing over I2C with the driver?).

[trejan]

I expect autodetection would be via I2C like the Poe HATs. The prototype M.2 HAT has a fan connector and current sensing so that'll be via I2C as well if it ends up in the release board. I don't know how much of this is implemented in the public firmware though.

Adding a couple pullup resistors might make it show some activity during startup.

[m1geo]

Will give that a shot. I'm just looking at the kernel & DT overlay source on the Pi5 GitHub. See if I can work out a way to tell SCL vs SDA when there's no data/clock on the bus.

[trejan]

Pull up only 1 and see what changes in pinctrl?

[m1geo]

Using pinctrl as suggested by @trejan the following can be observed:

Pulling P3 high:

$ diff idle.txt p3_high.txt
< 114: a1    pd | lo // PCIE_SDA/GPIO14 = SPI_S_MOSI_OR_BSC_S_SDA
> 114: a1    pd | hi // PCIE_SDA/GPIO14 = SPI_S_MOSI_OR_BSC_S_SDA

Pulling P4 high:

$ diff idle.txt p4_high.txt
< 28: no    pd | lo // PCIE_RP1_WAKE/GPIO28 = none
> 28: no    pd | hi // PCIE_RP1_WAKE/GPIO28 = none
< 115: a1    pd | lo // PCIE_SCL/GPIO15 = SPI_S_SCK_OR_BSC_S_SCL
> 115: a1    pd | hi // PCIE_SCL/GPIO15 = SPI_S_SCK_OR_BSC_S_SCL

Interesting that the PCIE_WAKE signal appears to be trigged with the clock being high. Taking this literally, a low BSC_S_SCL/GPIO15 indicates the PCIE_nWAKE request, too? Perhaps the signalling is to use the I2C clock stretching condition to signal a wake?

Couldn't get any life out of P1 and P2. Grounding P2 resulted in no difference from pinctrl. I was hoping it may have triggered RP1_PCIE_CLKREQ_N (as below) but nothing.

36: no pd | lo // RP1_PCIE_CLKREQ_N/GPIO36 = none

P3=PCIE_SDA
P4=PCIE_SCL (and WAKE?)

Closing ticket. I2C pins identified. Thanks for the help @trejan!

[m1geo]

Looking at the official Pi5 PCIe documentation,

P4=PCIE_SCL and WAKE is correct.
P3=PCIE_SDA also appears to serve as a PWR_EN signal.