drm/omap: Fix shmem write-combined buffer handling

Commit 7cb0d6c ("drm/omap: fix TILER on OMAP5") describes we can use
write-combined shmem mapping for the tiler for omap4. For omap5 it needs
to be uncached shmem mapping.

We currently have omap_gem_is_cached_coherent() block page faulting for
omap4 shmem write-combined buffer because of incomplete cache check.
We need to test for both OMAP_BO_CACHED and OMAP_BO_WC instead of just
OMAP_BO_CACHED.

Signed-off-by: Tony Lindgren <tony@atomide.com>

drivers/gpu/drm/omapdrm/omap_gem.c

@@ -691,9 +691,16 @@ int omap_gem_roll(struct drm_gem_object *obj, u32 roll)
 static inline bool omap_gem_is_cached_coherent(struct drm_gem_object *obj)
 {
 	struct omap_gem_object *omap_obj = to_omap_bo(obj);
+	u32 mask;
 
-	return !((omap_obj->flags & OMAP_BO_MEM_SHMEM) &&
-		((omap_obj->flags & OMAP_BO_CACHE_MASK) == OMAP_BO_CACHED));
+	if (!(omap_obj->flags & OMAP_BO_MEM_SHMEM))
+		return true;
+
+	mask = omap_obj->flags & OMAP_BO_CACHE_MASK;
+	if (mask == OMAP_BO_WC || mask == OMAP_BO_CACHED)
+		return false;
+
+	return true;
 }
 
 /* Sync the buffer for CPU access.. note pages should already be