Pinned Loading

1. ATPG_Tool_with-UI ATPG_Tool_with-UI Public

   Creating a end to end Open source Tool. Runs ATPG Algorithm(PODEM), Testablilty measures(SCOAP Analysis) for the Circuit created by user in Graphical User Interface

   1

2. mytools mytools Public

   Trying to learn new tools

   SourcePawn

3. RTL_to_GDSII_Adder RTL_to_GDSII_Adder Public

   RTL to GDSII of a 64bit Adder

   Verilog

4. Single_Cycle_Processor Single_Cycle_Processor Public

   A single cycle CPU has been constructed in Verilog.

   Verilog 1

5. i2c i2c Public

   The several codes i have seen so far uses sequential execution of the scl and sda and therefore sda changes when scl is at the edge.But in my code the sda changes only when scl is exactly at zero(L…

   Verilog 1

6. 16EC7G4 16EC7G4 Public

   VLSI Testing for ICs