/
namcos2.cpp
5797 lines (4634 loc) · 326 KB
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namcos2.cpp
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// license:BSD-3-Clause
// copyright-holders:K.Wilkins
/***************************************************************************
Namco System II driver by K.Wilkins (Jun1998, Oct1999)
Email: mame@esplexo.co.uk
How to calibrate the guns:
- hold 9, press f2
- shoot at the targets it shows using the crosshair
- after you've shot the target press 9 again to move onto the next one
- once you get back to the start again press f2 to exit.
How to calibrate the steering in Dirt Fox and Final Lap 2/3:
- hold 9, press f2
- verify that controls are set to zero then press f2 to exit.
Final Lap Notes:
1..4 cabinets may be wired together.
To move through self test options, press gas pedal and change gear shift from low to high
To change an option, move gear shift from low to high without touching the gas pedal
known issues:
- sprite/tilemap orthogonality needed
- bad road colors in Final Lap and Suzuka series
Final Lap & Final Lap 2:
- by default, the graphics are way too bright if compared to original PCB/monitor output
Finest Hour:
- roz plane colors are bad in-game
Final Lap 3:
- uses unaligned 32x32 sprites, which aren't handled correctly in video/namcos2.cpp yet
Suzuka 8 Hours II
- some sprite cropping issues
Valkyrie no Densetsu
- gives ADSMISS error on startup
Does a checksum on area 0x181000 - 0x183fff, in 0x20 bytes block chunks. Game doesn't init it properly so you either have to go into service menu and do
an "all data clear" or play once to get rid of the message.
Bubble Trouble (Golly Ghost II)
- no artwork
Metal Hawk
- ROZ wraparound isn't implemented
The Namco System II board is a 5 ( only 4 are emulated ) CPU system. The
complete system consists of two boards: CPU + GRAPHICS. It contains a large
number of custom ASICs to perform graphics operations, there is no
documentation available for these parts.
The system is extremely powerful and flexible. A standard CPU board is coupled
with a number of different graphics boards to produce a system.
CPU Board details
=================
CPU BOARD - Master/Slave CPU, Sound CPU, I/O CPU, Serial I/F CPU
Text/Scrolling layer generation and video pixel generator.
Sound Generation.
CPU1 - Master CPU (68K)
CPU2 - Slave CPU (68K)
CPU3 - Sound/IO engine (6809)
CPU4 - IO Microcontroller (63705) Dips/input ports
CPU5 - Serial I/F Controller (??? - Not emulated)
The 4 CPU's are all connected via a central 2KByte dual port SRAM. The two
68000s are on one side and the 6809/63705 are on the other side.
Each 68000 has its own private bus area AND a common shared area between the
two devices, which is where the video ram/dual port/Sprite Generation etc
logic sits.
So far only 1 CPU board variant has been identified, unlike the GFX board...
All sound circuitry is contained on the CPU board, it consists of:
YM2151
C140 (24 Channel Stereo PCM Sample player)
The CPU board also contains the frame timing and video image generation
circuitry along with text/scroll planes and the palette generator. The system
has 8192 pens of which 4096+2048 are displayable at any given time. These
pens reference a 24 bit colour lookup table (R8:G8:B8).
The text/tile plane generator has the following capabilities:
2 x Static tile planes (36x28 tiles)
4 x Scrolling tile planes (64x64 tiles)
Each plane has its own colour index (8 total) that is used alongside the
pen number to be looked up in the pen index and generate a 24 bit pixel. Each
plane also has its own priority level.
The video image generator receives a pixel stream from the graphics board
which contains:
PEN NUMBER
COLOUR BANK
PIXEL PRIORITY
This stream is then combined with the stream from the text plane pixel
generator with the highest priority pixel being displayed on screen.
Graphics Board details
======================
There are several variants of graphics board with unique capabilities
separate memory map definition. The PCB outputs a pixel stream to the
main PCB board via one of the system connectors.
ROZ(A): 1 256x256 ROZ plane composed of 8x8 tiles
ROZ(B): 2 ROZ planes, composed of 16x16 tiles (same as Namco NB2)
Sprite(A): 128 Sprites displayable, but 16 banks of 128 sprites
Sprite(B): (same as Namco NB2)
Roadway: tiles and road attributes in RAM
ROZ Sprites Roadway
Standard Namco System 2 (A) (A) n/a
Final Lap (1/2/3) n/a (A) yes
Metal Hawk (B) (A) no
Steel Gunner 2 n/a (B) no
Suzuka (1/2) n/a (B) yes
Lucky&Wild (B) (B) yes
Memory Map
==========
The Dual 68000 Shared memory map area is shown below, this is taken from the memory
decoding pal from the Cosmo Gang board.
#############################################################
# #
# MASTER 68000 PRIVATE MEMORY AREA (MAIN PCB) #
# #
#############################################################
# Function Address R/W DATA #
#############################################################
Program ROM 000000-03FFFF R D00-D15
Program RAM 100000-10FFFF R/W D00-D15
EEPROM 180000-183FFF R/W D00-D07
Interrupt Controller C148 1C0000-1FFFFF R/W D00-D02
???????? 1C0XXX
???????? 1C2XXX
???????? 1C4XXX
Master/Slave IRQ level 1C6XXX D00-D02
EXIRQ level 1C8XXX D00-D02
POSIRQ level 1CAXXX D00-D02
SCIRQ level 1CCXXX D00-D02
VBLANK IRQ level 1CEXXX D00-D02
???????? 1D0XXX
???????? 1D4000 trigger master/slave INT?
Acknowledge Master/Slave IRQ 1D6XXX ack master/slave INT
Acknowledge EXIRQ 1D8XXX
Acknowledge POSIRQ 1DAXXX
Acknowledge SCIRQ 1DCXXX
Acknowledge VBLANK IRQ 1DEXXX
EEPROM Ready status 1E0XXX R D01
Sound CPU Reset control 1E2XXX W D01
Slave 68000 & IO CPU Reset 1E4XXX W D01
Watchdog reset kicker 1E6XXX W
#############################################################
# #
# SLAVE 68000 PRIVATE MEMORY AREA (MAIN PCB) #
# #
#############################################################
# Function Address R/W DATA #
#############################################################
Program ROM 000000-03FFFF R D00-D15
Program RAM 100000-10FFFF R/W D00-D15
Interrupt Controller C148 1C0000-1FFFFF R/W D00-D02
???????? 1C0XXX
???????? 1C2XXX
???????? 1C4XXX
Master/Slave IRQ level 1C6XXX D00-D02
EXIRQ level 1C8XXX D00-D02
POSIRQ level 1CAXXX D00-D02
SCIRQ level 1CCXXX D00-D02
VBLANK IRQ level 1CEXXX D00-D02
???????? 1D0XXX
Acknowledge Master/Slave IRQ 1D6XXX
Acknowledge EXIRQ 1D8XXX
Acknowledge POSIRQ 1DAXXX
Acknowledge SCIRQ 1DCXXX
Acknowledge VBLANK IRQ 1DEXXX
Watchdog reset kicker 1E6XXX W
#############################################################
# #
# SHARED 68000 MEMORY AREA (MAIN PCB) #
# #
#############################################################
# Function Address R/W DATA #
#############################################################
Data ROMS 0-1 200000-2FFFFF R D00-D15
Data ROMS 2-3 300000-3FFFFF R D00-D15
Screen memory for text planes 400000-41FFFF R/W D00-D15
Screen control registers 420000-43FFFF R/W D00-D15
Scroll plane 0 - X offset 42XX02 W D00-D11
Scroll plane 0 - X flip 42XX02 W D15
?????? 42XX04 W D14-D15
Scroll plane 0 - Y offset 42XX06 W D00-D11
Scroll plane 0 - Y flip 42XX06 W D15
?????? 42XX08 W D14-D15
Scroll plane 1 - X offset 42XX0A W D00-D11
Scroll plane 1 - X flip 42XX0A W D15
?????? 42XX0C W D14-D15
Scroll plane 1 - Y offset 42XX0E W D00-D11
Scroll plane 1 - Y flip 42XX0E W D15
?????? 42XX10 W D14-D15
Scroll plane 2 - X offset 42XX12 W D00-D11
Scroll plane 2 - X flip 42XX12 W D15
?????? 42XX14 W D14-D15
Scroll plane 2 - Y offset 42XX16 W D00-D11
Scroll plane 2 - Y flip 42XX16 W D15
?????? 42XX18 W D14-D15
Scroll plane 3 - X offset 42XX1A W D00-D11
Scroll plane 3 - X flip 42XX1A W D15
?????? 42XX1C W D14-D15
Scroll plane 3 - Y offset 42XX1E W D00-D11
Scroll plane 3 - Y flip 42XX1E W D15
Scroll plane 0 priority 42XX20 W D00-D02
Scroll plane 1 priority 42XX22 W D00-D02
Scroll plane 2 priority 42XX24 W D00-D02
Scroll plane 3 priority 42XX26 W D00-D02
Text plane 0 priority 42XX28 W D00-D02
Text plane 1 priority 42XX2A W D00-D02
Scroll plane 0 colour 42XX30 W D00-D03
Scroll plane 1 colour 42XX32 W D00-D03
Scroll plane 2 colour 42XX34 W D00-D03
Scroll plane 3 colour 42XX36 W D00-D03
Text plane 0 colour 42XX38 W D00-D03
Text plane 1 colour 42XX3A W D00-D03
Screen palette control/data 440000-45FFFF R/W D00-D15
RED ROZ/Sprite pens 8x256 440000-440FFF
GREEN 441000-441FFF
BLUE 442000-442FFF
Control registers 443000-44300F R/W D00-D15
RED ROZ/Sprite pens 8x256 444000-444FFF
GREEN 445000-445FFF
BLUE 446000-446FFF
447000-447FFF
RED Text plane pens 8x256 448000-448FFF
GREEN 449000-449FFF
BLUE 44A000-44AFFF
44B000-44BFFF
RED Unused pens 8x256 44C000-44CFFF
GREEN 44D000-44DFFF
BLUE 44E000-44EFFF
Dual port memory 460000-47FFFF R/W D00-D07
Serial comms processor 480000-49FFFF
Serial comms processor - Data 4A0000-4BFFFF
#############################################################
# #
# SHARED 68000 MEMORY AREA (GFX PCB) #
# (STANDARD NAMCO SYSTEM 2 BOARD) #
# #
#############################################################
# Function Address R/W DATA #
#############################################################
Sprite RAM - 16 banks x 128 spr. C00000-C03FFF R/W D00-D15
Sprite bank select C40000 W D00-D03
Rotate colour bank select W D08-D11
Rotate priority level W D12-D14
Rotate/Zoom RAM (ROZ) C80000-CBFFFF R/W D00-D15
Rotate/Zoom - Down dy (8:8) CC0000 R/W D00-D15
Rotate/Zoom - Right dy (8.8) CC0002 R/W D00-D15
Rotate/Zoom - Down dx (8.8) CC0004 R/W D00-D15
Rotate/Zoom - Right dx (8.8) CC0006 R/W D00-D15
Rotate/Zoom - Start Ypos (12.4) CC0008 R/W D00-D15
Rotate/Zoom - Start Xpos (12.4) CC000A R/W D00-D15
Rotate/Zoom control CC000E R/W D00-D15
Key generator/Security device D00000-D0000F R/W D00-D15
#############################################################
# #
# SHARED 68000 MEMORY AREA (GFX PCB) #
# (METAL HAWK PCB - DUAL ROZ PLANES) #
# #
#############################################################
# Function Address R/W DATA #
#############################################################
Sprite RAM - 16 banks x 128 spr. C00000-C03FFF R/W D00-D15
Rotate/Zoom RAM (ROZ1) C40000-C47FFF R/W D00-D15
Rotate/Zoom RAM (ROZ2) C48000-C4FFFF R/W D00-D15
Rotate/Zoom1 - Down dy (8:8) D00000 R/W D00-D15
Rotate/Zoom1 - Right dy (8.8) D00002 R/W D00-D15
Rotate/Zoom1 - Down dx (8.8) D00004 R/W D00-D15
Rotate/Zoom1 - Right dx (8.8) D00006 R/W D00-D15
Rotate/Zoom1 - Start Ypos (12.4) D00008 R/W D00-D15
Rotate/Zoom1 - Start Xpos (12.4) D0000A R/W D00-D15
Rotate/Zoom1 - control D0000E R/W D00-D15
Rotate/Zoom2 - Down dy (8:8) D00010 R/W D00-D15
Rotate/Zoom2 - Right dy (8.8) D00012 R/W D00-D15
Rotate/Zoom2 - Down dx (8.8) D00014 R/W D00-D15
Rotate/Zoom2 - Right dx (8.8) D00016 R/W D00-D15
Rotate/Zoom2 - Start Ypos (12.4) D00018 R/W D00-D15
Rotate/Zoom2 - Start Xpos (12.4) D0001A R/W D00-D15
Rotate/Zoom2 - control D0001E R/W D00-D15
Sprite bank select ? E00000 W D00-D15
#############################################################
# #
# SHARED 68000 MEMORY AREA (GFX PCB) #
# (FINAL LAP PCB) #
# #
#############################################################
# Function Address R/W DATA #
#############################################################
Sprite RAM - ?? banks x ??? spr. 800000-80FFFF R/W D00-D15
Sprite bank select ? 840000 W D00-D15
Road RAM for tile layout 880000-88FFFF R/W D00-D15
Road RAM for tiles gfx data 890000-897FFF R/W D00-D15
Road Generator controls 89F000-89FFFF R/W D00-D15
Key generator/Security device A00000-A0000F R/W D00-D15
All interrupt handling is done on the 68000s by two identical custom devices (C148),
this device takes the level based signals and encodes them into the 3 bit encoded
form for the 68000 CPU. The master CPU C148 also controls the reset for the slave
CPU and MCU which are common. The C148 only has the lower 3 data bits connected.
C148 Features
-------------
3 Bit output port
3 Bit input port
3 Chip selects
68000 Interrupt encoding/handling
Data strobe control
Bus arbitration
Reset output
Watchdog
C148pin Master CPU Slave CPU
-------------------------------------
YBNK VBLANK VBLANK
IRQ4 SCIRQ SCIRQ (Serial comms IC Interrupt)
IRQ3 POSIRQ POSIRQ (Comes from C116, pixel generator, line based position interrupt?)
IRQ2 EXIRQ EXIRQ (Goes to video board but does not appear to be connected)
IRQ1 SCPUIRQ MCPUIRQ (Master/Slave interrupts)
OP0 SSRES (Sound CPU reset - 6809 only)
OP1
OP2
IP0 EEPROM BUSY
IP1
IP2
Protection
----------
The Chip at $d00000 seems to be heavily involved in protection, some games lock
or reset if it doesn't return the correct values.
rthun2 is sprinkled with reads to $d00006 which look like they are being used as
random numbers. rthun2 also checks the response value after a number is written.
Device takes clock and vblank. Only output is reset.
This chip is based on the graphics board.
Palette
-------
0x800 (2048) colours
Ram test does:
$440000-$442fff Object ???
$444000-$446fff Char ???
$448000-$44afff Roz ???
$44c000-$44efff
$448000-$4487ff Red??
$448800-$448fff Green??
$449000-$4497ff Blue??
Steel Gunner 2
--------------
Again this board has a different graphics layout, also the protection checks
are done at $a00000 as opposed to $d00000 on a standard board. Similar
$a00000 checks have been seen on the Final Lap boards.
Custom Chips Notes (moved to here from Stroff's old namcoic.c)
==================
System 21 here presumably refers to the Winning Run PCB, not the later games?
Custom Chips: Final Lap Assault LuckyWld System21 NA1/2 NB1/2
C45 Land Generator * *
C65 I/O Controller (older) * *
C67 TMS320C25 (DSP int ROM)
C68 I/O Controller (newer) * *
C70 *
C95 * *
C102 ROZ:Memory Access Control *
C106 OBJ:X-Axis Zoom Control * *
C107 Land Line Buffer *
C116 Screen Waveform Generator * * * *
C121 Yamaha YM2151 Sound Gen * * *
C123 GFX:Tile Mem Decoder * * * *
C134 OBJ:Address Generator * *
C135 OBJ:Line matching * *
C137 Clock Generator IC * * * * *
C138 *
C139 Serial I/F Controller * * * *
C140 24 Channel PCM * * *
C145 GFX:Tile Memory Access * * * *
C146 OBJ:Line Buf Steering * *
C148 CPU Bus Manager * * * *
C149 Mouse/Trackball Decoder * * * *
C156 Pixel Stream Combo * * * *
C160 Control *
C165 *
C169 ROZ(B) * *
C187 * * *
C210 *
C215 *
C218 *
C219 *
C329 CPU? *
C347 GfxObj *
C352 PCM *
C355 Motion Obj(B) * * *
C373 LAND-related *
C382 *
C383 *
C384 GFX(3) *
C385 *
C390 Key Custom *
General Support
---------------
C65 - This is the I/O Microcontroller, handles all input/output devices. 63705 uC, CPU4 in Namco System2.
C137 - Takes System clock and generates all sub-system clocks, doesn't need emulation, not accessed via CPU
C139 - Serial Interface Controller
C148 - Does some Memory Decode, Interrupt Handling, 3 bit PIO port, Bus Controller
C149 - Does decoding of mouse/trackball input streams for the I/O Controller. (Offset Square wave)
Tile Fields Static/Scrolled
---------------------------
Combination of these two devices and associated RAM & TileGFX produces a pixel stream that is fed
into the Pixel stream decoder.
C145 - Tile Screen Memory Access controller
C123 - Tile Memory decoder Part 1, converts X,Y,Tile into character ROM address index
Pixel Stream Decode
-------------------
These two devices take the pixel streams from the tilefield generator and the associated graphics board
and combine them to form an RGB data stream that is fed to the monitor.
C156 - Pixel stream combiner
Takes tile field & graphics board streams and generates the prioritized pixel, then does the lookup to
go from palettised to 24bit RGB pixel.
C116 - Screen Waveform Generator
Takes RGB24 pixel stream from C156 and generates the waveform signals for the monitor, also generates
the line interrupt and controls screen blanking,shift, etc.
Object Control
--------------
C106 - Generates memory output clocks to generate X-Axis Zoom for Line Buffer Writes
C134 - Object Memory Address Generator. Sequences the sprite memory contents to the hardware.
C135 - Checks is object is displayed on Current output line.
C146 - Steers the Decode Object Pixel data to the correct line buffer A or B
ROZ
---
C102 - Controls CPU access to ROZ Memory Area.
***************************************************************************/
#include "emu.h"
#include "includes/namcos2.h"
#include "cpu/m68000/m68000.h"
#include "cpu/m6805/m6805.h"
#include "cpu/m6809/m6809.h"
#include "machine/nvram.h"
#include "sound/ymopm.h"
#include "speaker.h"
#include "finallap.lh"
/* Define clocks based on actual OSC on the PCB */
#define MAIN_OSC_CLOCK XTAL(49'152'000)
#define M68K_CPU_CLOCK (MAIN_OSC_CLOCK / 4) /* 12.288MHz clock for 68000 (Master & Slave) */
#define M68B09_CPU_CLOCK (MAIN_OSC_CLOCK / 24) /* 2.048MHz clock for 68B09 sound CPU */
#define C65_CPU_CLOCK (MAIN_OSC_CLOCK / 24) /* 2.048MHz clock for 63705 (or 63B05) I/O CPU */
#define C68_CPU_CLOCK (MAIN_OSC_CLOCK / 6) /* 8.192MHz clock for 37450 I/O CPU */
#define YM2151_SOUND_CLOCK XTAL(3'579'545) /* 3.579545MHz FM clock */
#define C140_SOUND_CLOCK (MAIN_OSC_CLOCK / 384 / 6) /* 21.333kHz C140 clock (was 8000000/374 or 21.390kHz) */
/*************************************************************/
/* 68000/6809/63705 Shared memory area - DUAL PORT Memory */
/*************************************************************/
void namcos2_state::GollyGhostUpdateLED_c4(int data)
{
output().set_value("zip100", data >> 4);
output().set_value("zip10", data & 0x0f);
}
void namcos2_state::GollyGhostUpdateLED_c6(int data)
{
output().set_value("zip1", data >> 4);
output().set_value("time10", data & 0x0f);
}
void namcos2_state::GollyGhostUpdateLED_c8(int data)
{
output().set_value("time1", data >> 4);
output().set_value("zap100", data & 0x0f);
}
void namcos2_state::GollyGhostUpdateLED_ca(int data)
{
output().set_value("zap10", data >> 4);
output().set_value("zap1", data & 0x0f);
}
void namcos2_state::GollyGhostUpdateDiorama_c0(int data)
{
if (data & 0x80)
{
output().set_value("dollhouse", 1); /* diorama is lit up */
/* dollhouse controller; solenoids control physical components */
output().set_value("toybox", (data >> 0) & 1);
output().set_value("bathroom", (data >> 1) & 1);
output().set_value("bureau", (data >> 2) & 1);
output().set_value("refrigerator",(data >> 3) & 1);
output().set_value("porch", (data >> 4) & 1);
/* gun recoils */
output().set_value("Player1_Gun_Recoil",(data & 0x20)>>5);
output().set_value("Player2_Gun_Recoil",(data & 0x40)>>6);
}
else
{
output().set_value("dollhouse",0);
output().set_value("toybox", 0);
output().set_value("bathroom", 0);
output().set_value("bureau", 0);
output().set_value("refrigerator", 0);
output().set_value("porch", 0);
output().set_value("Player1_Gun_Recoil",0);
output().set_value("Player2_Gun_Recoil",0);
}
}
uint16_t namcos2_state::dpram_word_r(offs_t offset)
{
return m_dpram[offset];
}
void namcos2_state::dpram_word_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if( ACCESSING_BITS_0_7 )
{
m_dpram[offset] = data&0xff;
// TODO : This is a hack! should be output ports MCU side, not probing into DPRAM content
if( m_gametype==NAMCOS2_GOLLY_GHOST )
{
switch( offset )
{
case 0xc0/2: GollyGhostUpdateDiorama_c0(data); break;
case 0xc2/2:
/* unknown; 0x00 or 0x01 - probably lights up guns */
break;
case 0xc4/2: GollyGhostUpdateLED_c4(data); break;
case 0xc6/2: GollyGhostUpdateLED_c6(data); break;
case 0xc8/2: GollyGhostUpdateLED_c8(data); break;
case 0xca/2: GollyGhostUpdateLED_ca(data); break;
default:
break;
}
}
/* Note: Outputs for the other gun games pass through here as well, but I couldn't find the offsets. */
/* Steel Gunner 1 & 2 have 6 "damage lamps" (three on each side) as well as gun recoils. */
}
}
uint8_t namcos2_state::dpram_byte_r(offs_t offset)
{
return m_dpram[offset];
}
void namcos2_state::dpram_byte_w(offs_t offset, uint8_t data)
{
m_dpram[offset] = data;
}
/*************************************************************/
/* SHARED 68000 CPU Memory declarations */
/*************************************************************/
/* ROM0 = $200000-$2fffff
ROM1 = $300000-$3fffff
SCR = $400000-$41ffff
SCRDT = $420000-$43ffff
PALET = $440000-$45ffff
DPCS = $460000-$47ffff
SCOM = $480000-$49ffff
SCOMDT = $4a0000-$4bffff
0xc00000 ONWARDS are unverified memory locations on the video board
*/
void namcos2_state::namcos2_68k_default_cpu_board_am(address_map &map)
{
map(0x200000, 0x3fffff).rom().region("data_rom", 0);
map(0x400000, 0x40ffff).mirror(0x010000).rw(m_c123tmap, FUNC(namco_c123tmap_device::videoram16_r), FUNC(namco_c123tmap_device::videoram16_w));
map(0x420000, 0x42003f).rw(m_c123tmap, FUNC(namco_c123tmap_device::control16_r), FUNC(namco_c123tmap_device::control16_w));
map(0x440000, 0x44ffff).r(FUNC(namcos2_state::c116_r)).w(m_c116, FUNC(namco_c116_device::write)).umask16(0x00ff).cswidth(16);
map(0x460000, 0x460fff).mirror(0x00f000).rw(FUNC(namcos2_state::dpram_word_r), FUNC(namcos2_state::dpram_word_w));
map(0x480000, 0x483fff).rw(m_sci, FUNC(namco_c139_device::ram_r), FUNC(namco_c139_device::ram_w));
map(0x4a0000, 0x4a000f).m(m_sci, FUNC(namco_c139_device::regs_map));
}
/*************************************************************/
void namcos2_state::common_default_am(address_map &map)
{
namcos2_68k_default_cpu_board_am(map);
map(0xc00000, 0xc03fff).ram().share("spriteram");
map(0xc40000, 0xc40001).rw(FUNC(namcos2_state::gfx_ctrl_r), FUNC(namcos2_state::gfx_ctrl_w));
map(0xc80000, 0xc9ffff).ram().w(m_ns2roz, FUNC(namcos2_roz_device::rozram_word_w)).share("rozram");
map(0xcc0000, 0xcc000f).ram().share("rozctrl");
map(0xd00000, 0xd0000f).rw(FUNC(namcos2_state::namcos2_68k_key_r), FUNC(namcos2_state::namcos2_68k_key_w));
}
void namcos2_state::master_common_am(address_map &map)
{
map(0x000000, 0x03ffff).rom();
map(0x100000, 0x10ffff).ram();
map(0x180000, 0x183fff).rw(FUNC(namcos2_state::eeprom_r), FUNC(namcos2_state::eeprom_w)).umask16(0x00ff);
map(0x1c0000, 0x1fffff).m(m_master_intc, FUNC(namco_c148_device::map));
}
void namcos2_state::slave_common_am(address_map &map)
{
map(0x000000, 0x03ffff).rom();
map(0x100000, 0x13ffff).ram();
map(0x1c0000, 0x1fffff).m(m_slave_intc, FUNC(namco_c148_device::map));
}
void namcos2_state::master_default_am(address_map &map)
{
common_default_am(map);
master_common_am(map);
}
void namcos2_state::slave_default_am(address_map &map)
{
common_default_am(map);
slave_common_am(map);
}
/*************************************************************/
void namcos2_state::common_finallap_am(address_map &map)
{
namcos2_68k_default_cpu_board_am(map);
map(0x300000, 0x33ffff).r(FUNC(namcos2_state::namcos2_finallap_prot_r));
map(0x800000, 0x80ffff).ram().share("spriteram");
map(0x840000, 0x840001).rw(FUNC(namcos2_state::gfx_ctrl_r), FUNC(namcos2_state::gfx_ctrl_w));
map(0x880000, 0x89ffff).rw(m_c45_road, FUNC(namco_c45_road_device::read), FUNC(namco_c45_road_device::write));
map(0x8c0000, 0x8c0001).nopw();
}
void namcos2_state::master_finallap_am(address_map &map)
{
common_finallap_am(map);
master_common_am(map);
}
void namcos2_state::slave_finallap_am(address_map &map)
{
common_finallap_am(map);
slave_common_am(map);
}
/*************************************************************/
void namcos2_state::common_sgunner_am(address_map &map)
{
namcos2_68k_default_cpu_board_am(map);
map(0x800000, 0x8141ff).rw(m_c355spr, FUNC(namco_c355spr_device::spriteram_r), FUNC(namco_c355spr_device::spriteram_w));
map(0x818000, 0x818001).nopw();
map(0xa00000, 0xa0000f).rw(FUNC(namcos2_state::namcos2_68k_key_r), FUNC(namcos2_state::namcos2_68k_key_w));
}
void namcos2_state::master_sgunner_am(address_map &map)
{
common_sgunner_am(map);
master_common_am(map);
}
void namcos2_state::slave_sgunner_am(address_map &map)
{
common_sgunner_am(map);
slave_common_am(map);
}
/*************************************************************/
void namcos2_state::common_metlhawk_am(address_map &map)
{
namcos2_68k_default_cpu_board_am(map);
map(0xc00000, 0xc03fff).ram().share("spriteram");
map(0xc40000, 0xc4ffff).rw(m_c169roz, FUNC(namco_c169roz_device::videoram_r), FUNC(namco_c169roz_device::videoram_w));
map(0xd00000, 0xd0001f).rw(m_c169roz, FUNC(namco_c169roz_device::control_r), FUNC(namco_c169roz_device::control_w));
map(0xe00000, 0xe00001).rw(FUNC(namcos2_state::gfx_ctrl_r), FUNC(namcos2_state::gfx_ctrl_w)); /* ??? */
}
void namcos2_state::master_metlhawk_am(address_map &map)
{
common_metlhawk_am(map);
master_common_am(map);
}
void namcos2_state::slave_metlhawk_am(address_map &map)
{
common_metlhawk_am(map);
slave_common_am(map);
}
/*************************************************************/
void namcos2_state::common_suzuka8h_am(address_map &map)
{
namcos2_68k_default_cpu_board_am(map);
map(0x800000, 0x8141ff).rw(m_c355spr, FUNC(namco_c355spr_device::spriteram_r), FUNC(namco_c355spr_device::spriteram_w));
map(0x818000, 0x818001).noprw(); /* enable? */
map(0x81a000, 0x81a001).nopw(); /* enable? */
map(0x840000, 0x840001).nopr();
map(0x900000, 0x900007).rw(m_c355spr, FUNC(namco_c355spr_device::position_r), FUNC(namco_c355spr_device::position_w));
map(0xa00000, 0xa1ffff).rw(m_c45_road, FUNC(namco_c45_road_device::read), FUNC(namco_c45_road_device::write));
map(0xf00000, 0xf00007).rw(FUNC(namcos2_state::namcos2_68k_key_r), FUNC(namcos2_state::namcos2_68k_key_w));
}
void namcos2_state::common_suzuka8h_roz_am(address_map &map)
{
map(0xc00000, 0xc0ffff).noprw(); // no ROZ hardware implemented in PCB
map(0xd00000, 0xd0001f).noprw(); // ^^
}
void namcos2_state::master_suzuka8h_am(address_map &map)
{
common_suzuka8h_am(map);
master_common_am(map);
common_suzuka8h_roz_am(map);
}
void namcos2_state::slave_suzuka8h_am(address_map &map)
{
common_suzuka8h_am(map);
slave_common_am(map);
common_suzuka8h_roz_am(map);
}
void namcos2_state::common_luckywld_roz_am(address_map &map)
{
map(0xc00000, 0xc0ffff).rw(m_c169roz, FUNC(namco_c169roz_device::videoram_r), FUNC(namco_c169roz_device::videoram_w));
map(0xd00000, 0xd0001f).rw(m_c169roz, FUNC(namco_c169roz_device::control_r), FUNC(namco_c169roz_device::control_w));
}
void namcos2_state::master_luckywld_am(address_map &map)
{
common_suzuka8h_am(map);
master_common_am(map);
common_luckywld_roz_am(map);
}
void namcos2_state::slave_luckywld_am(address_map &map)
{
common_suzuka8h_am(map);
slave_common_am(map);
common_luckywld_roz_am(map);
}
/*************************************************************/
/* 6809 SOUND CPU Memory declarations */
/*************************************************************/
void namcos2_state::sound_default_am(address_map &map)
{
map(0x0000, 0x3fff).bankr("audiobank"); /* banked */
map(0x4000, 0x4001).rw("ymsnd", FUNC(ym2151_device::read), FUNC(ym2151_device::write));
map(0x5000, 0x51ff).mirror(0x0e00).rw(m_c140, FUNC(c140_device::c140_r), FUNC(c140_device::c140_w));
map(0x6000, 0x61ff).mirror(0x0e00).rw(m_c140, FUNC(c140_device::c140_r), FUNC(c140_device::c140_w)); // mirrored
map(0x7000, 0x77ff).mirror(0x0800).rw(FUNC(namcos2_state::dpram_byte_r), FUNC(namcos2_state::dpram_byte_w)).share("dpram");
map(0x8000, 0x9fff).ram();
map(0xa000, 0xbfff).nopw(); /* Amplifier enable on 1st write */
map(0xc000, 0xc001).w(FUNC(namcos2_state::sound_bankselect_w));
map(0xd001, 0xd001).nopw(); /* Watchdog */
map(0xe000, 0xe000).nopw();
map(0xd000, 0xffff).rom().region("audiocpu", 0x01000);
}
void namcos2_state::c140_default_am(address_map &map)
{
map.global_mask(0x7fffff); // bit 23-24 not connected
map(0x000000, 0x7fffff).r(FUNC(namcos2_state::c140_rom_r));
}
/*************************************************************/
/* */
/* NAMCO SYSTEM 2 PORT MACROS */
/* */
/* Below are the port definition macros that should be used */
/* as the basis for defining a port set for a Namco System2 */
/* game. */
/* */
/*************************************************************/
#define NAMCOS2_MCU_PORT_B_DEFAULT \
PORT_START("MCUB") /* 63B05Z0 - PORT B */ \
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2) \
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) \
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) \
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) \
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2) \
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) \
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START2 ) \
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
#define NAMCOS2_MCU_PORT_C_DEFAULT \
PORT_START("MCUC") /* 63B05Z0 - PORT C & SCI */ \
PORT_BIT( 0x0f, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 ) \
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 ) \
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("Service Button") \
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
#define NAMCOS2_MCU_ANALOG_PORT_DEFAULT \
PORT_START("AN0") /* 63B05Z0 - 8 CHANNEL ANALOG - CHANNEL 0 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_START("AN1") /* 63B05Z0 - 8 CHANNEL ANALOG - CHANNEL 1 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_START("AN2") /* 63B05Z0 - 8 CHANNEL ANALOG - CHANNEL 2 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_START("AN3") /* 63B05Z0 - 8 CHANNEL ANALOG - CHANNEL 3 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_START("AN4") /* 63B05Z0 - 8 CHANNEL ANALOG - CHANNEL 4 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_START("AN5") /* 63B05Z0 - 8 CHANNEL ANALOG - CHANNEL 5 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_START("AN6") /* 63B05Z0 - 8 CHANNEL ANALOG - CHANNEL 6 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_START("AN7") /* 63B05Z0 - 8 CHANNEL ANALOG - CHANNEL 7 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
#define NAMCOS2_MCU_PORT_H_DEFAULT \
PORT_START("MCUH") /* 63B05Z0 - PORT H */ \
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) \
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON3 ) \
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) \
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON2 ) \
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) \
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) \
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2) \
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
#define NAMCOS2_MCU_DIPSW_DEFAULT \
PORT_START("DSW") /* 63B05Z0 - $2000 DIP SW */ \
PORT_DIPNAME( 0x01, 0x01, "Video Display") \
PORT_DIPSETTING( 0x01, DEF_STR( Normal ) ) \
PORT_DIPSETTING( 0x00, "Frozen" ) \
PORT_DIPNAME( 0x02, 0x02, "$2000-1") \
PORT_DIPSETTING( 0x02, "H" ) \
PORT_DIPSETTING( 0x00, "L" ) \
PORT_DIPNAME( 0x04, 0x04, "$2000-2") \
PORT_DIPSETTING( 0x04, "H" ) \
PORT_DIPSETTING( 0x00, "L" ) \
PORT_DIPNAME( 0x08, 0x08, "$2000-3") \
PORT_DIPSETTING( 0x08, "H" ) \
PORT_DIPSETTING( 0x00, "L" ) \
PORT_DIPNAME( 0x10, 0x10, "$2000-4") \
PORT_DIPSETTING( 0x10, "H" ) \
PORT_DIPSETTING( 0x00, "L" ) \
PORT_DIPNAME( 0x20, 0x20, "$2000-5") \
PORT_DIPSETTING( 0x20, "H" ) \
PORT_DIPSETTING( 0x00, "L" ) \
PORT_DIPNAME( 0x40, 0x40, "$2000-6") \
PORT_DIPSETTING( 0x40, "H" ) \
PORT_DIPSETTING( 0x00, "L" ) \
PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
#define NAMCOS2_MCU_DIAL_DEFAULT \
PORT_START("MCUDI0") /* 63B05Z0 - $3000 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_START("MCUDI1") /* 63B05Z0 - $3001 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_START("MCUDI2") /* 63B05Z0 - $3002 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) \
PORT_START("MCUDI3") /* 63B05Z0 - $3003 */ \
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
/*************************************************************/
/* */
/* NAMCO SYSTEM 2 PORT DEFINITIONS */
/* */
/* There is a standard port definition defined that will */
/* work for most games, if you wish to produce a special */
/* definition for a particular game then see the assault */
/* and dirtfox definitions for examples of how to construct */
/* a special port definition */
/* */
/* The default definitions includes only the following list */
/* of connections : */
/* 2 Joysticks, 6 Buttons, 1 Service, 1 Advance */
/* 2 Start */
/* */
/*************************************************************/
static INPUT_PORTS_START( base )
NAMCOS2_MCU_PORT_B_DEFAULT
NAMCOS2_MCU_PORT_C_DEFAULT
NAMCOS2_MCU_ANALOG_PORT_DEFAULT
NAMCOS2_MCU_PORT_H_DEFAULT
NAMCOS2_MCU_DIPSW_DEFAULT
NAMCOS2_MCU_DIAL_DEFAULT