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cps3.cpp
3949 lines (3304 loc) · 179 KB
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cps3.cpp
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// license:BSD-3-Clause
// copyright-holders:David Haywood, Andreas Naive, Tomasz Slanina, ElSemi
/*
CPS3 Driver (preliminary)
Decryption by Andreas Naive
Driver by David Haywood
with help from Tomasz Slanina and ElSemi
Sound emulation by Philip Bennett
SCSI code by ElSemi
Known Issues:
Tilemap Global X/Y flip not emulated
Street Fighter 3 2nd Impact uses Y-flipped tilemaps during flashing.
Warzard uses X-flipped tilemaps during special effects.
Sprite-list caching (presumable)
Warzard 2p mode, at next screen after characters select,
if holding player's button to speed up sequence - player's sprites will be distorted.
Whole screen flip not emulated
Miscellaneous TO-DOs:
DMA ack IRQ10 generation:
Character and Palette DMAs speed is unknown, needs to be measured.
Alpha Blending Effects
These are actually palette manipulation effects, not true blending.
Verify them, current emulation might not be 100% accurate.
Tilemap Linezoom
Seems unused in games. May be enabled in jojo/jojoba dev.menu BG test (P2 btn4)
Palette DMA effects
Verify them, they might not be 100% accurate at the moment
Verify Full Screen Zoom on real hardware
How far can it zoom etc.
Verify CRT registers
Actual Pixel clock for H Start and H Blank registers is unknown. It is not known which is base pixel clock
and how it affected by register 40C0080 bits.
Sprite positioning glitches
Some sprites are still in the wrong places, seems the placement of zooming sprites is imperfect
eg. warzard intro + cutscenes leave the left most 16 pixels uncovered because the sprite is positioned incorrectly,
the same occurs in the sf games. doesn't look like the origin is correct when zooming in all cases.
Gaps in Sprite Zooming
Warzard is confirmed to have gaps during some cut-scenes on real hardware.
---
Capcom CP SYSTEM III Hardware Overview
Capcom, 1996-1999
From late 1996 to 1999 Capcom developed another hardware platform to rival the CPS2 System and called
it CP SYSTEM III. Only 6 games were produced. Here's a detailed table of all known releases until now:
|--------------- Cart ----------------| |-------------- CD ---------------|
Game Year Part # Label Region CD NO CD Part # Catalog # Label Revision
--------------------------------------------------- ---- --------- --------- ------ -- ----- ---------- ---------- ----------- --------
Warzard 1996 WZD96a00F CP300000G JAPAN X CAP-WZD000 CAP-WZD-3 CAP-WZD-3 961023
Warzard WZD96a00F CP300000G JAPAN X CAP-WZD000 CAP-WZD-5 CAP-WZD-5 961121
Red Earth WZD96aA0F CP3000B0G EUROPE X CAP-WZD0A0 CAP-WZD-3 CAP-WZD-3 961023
Red Earth WZD96aA0F CP3000B0G EUROPE X CAP-WZD0A0 CAP-WZD-5 CAP-WZD-5 961121
Red Earth WZD96aA0F CP3000H0G MEXICO* X CAP-WZD0A0 CAP-WZD-3 CAP-WZD-3 961023
Red Earth WZD96aA0F CP3000H0G MEXICO* X CAP-WZD0A0 CAP-WZD-5 CAP-WZD-5 961121
Red Earth WZD96aA0F CP3000U0G USA* X CAP-WZD0A0 CAP-WZD-3 CAP-WZD-3 961023
Red Earth WZD96aA0F CP3000U0G USA* X CAP-WZD0A0 CAP-WZD-5 CAP-WZD-5 961121
Street Fighter III: New Generation 1997 SF397200F CP300000G JAPAN X CAP-SF3000 CAP-SF3-3 CAP-SF3-3 970204
Street Fighter III: New Generation SF397200F CP300000G JAPAN X CAP-SF3000 ? ? 970312*
Street Fighter III: New Generation SF397200F CP300000G JAPAN X CAP-SF3000 ? ? 970403*
Street Fighter III: New Generation SF3972A0F CP3000B0G EUROPE X CAP-SF30A0 CAP-SF3-3 CAP-SF3-3 970204
Street Fighter III: New Generation SF3972A0F CP3000B0G EUROPE X CAP-SF30A0 ? ? 970312*
Street Fighter III: New Generation SF3972A0F CP3000B0G EUROPE X CAP-SF30A0 ? ? 970403*
Street Fighter III: New Generation SF3972A0F CP3000C0G ASIA X 970204
Street Fighter III: New Generation SF3972A0F CP3000C0G ASIA X 970312*
Street Fighter III: New Generation SF3972A0F CP3000C0G ASIA X 970403*
Street Fighter III: New Generation SF3972A0F CP3000H0G MEXICO X CAP-SF30A0 CAP-SF3-3 CAP-SF3-3 970204
Street Fighter III: New Generation SF3972A0F CP3000H0G MEXICO X CAP-SF30A0 ? ? 970312*
Street Fighter III: New Generation SF3972A0F CP3000H0G MEXICO X CAP-SF30A0 ? ? 970403*
Street Fighter III: New Generation SF3972A0F CP3000U0G USA X CAP-SF30A0 CAP-SF3-3 CAP-SF3-3 970204
Street Fighter III: New Generation SF3972A0F CP3000U0G USA X CAP-SF30A0 ? ? 970312*
Street Fighter III: New Generation SF3972A0F CP3000U0G USA X CAP-SF30A0 ? ? 970403*
Street Fighter III 2nd Impact: Giant Attack 1997 3GA97a00F CP300000G JAPAN X CAP-3GA000 CAP-3GA000 CAP-3GA-1 970930
Street Fighter III 2nd Impact: Giant Attack 3GA97a00F CP300000G JAPAN X CAP-3GA000 ? ? 971016*
Street Fighter III 2nd Impact: Giant Attack 3GA97aA0F CP3000C0G ASIA X 970930
Street Fighter III 2nd Impact: Giant Attack 3GA97aA0F CP3000C0G ASIA X 971016*
Street Fighter III 2nd Impact: Giant Attack 3GA97aA0F CP3000U0G USA X CAP-3GA0A0 CAP-3GA000 CAP-3GA-1 970930
Street Fighter III 2nd Impact: Giant Attack 3GA97aA0F CP3000U0G USA X CAP-3GA0A0 ? ? 971016*
JoJo no Kimyou na Bouken 1998 JJK98c00F CP300000G JAPAN X CAP-JJK000 CAP-JJK000 CAP-JJK-140 981202
JoJo no Kimyou na Bouken JJK98c00F CP300000G JAPAN X CAP-JJK000 CAP-JJK-2 CAP-JJK-160 990108
JoJo no Kimyou na Bouken JJK98c00F CP300000G JAPAN X CAP-JJK000 CAP-JJK-3 CAP-JJK-161 990128
JoJo's Venture JJK98cA0F CP3000C0G ASIA X 981202
JoJo's Venture JJK98cA0F CP3000C0G ASIA X 990108
JoJo's Venture JJK98cA0F CP3000C0G ASIA X 990128
JoJo's Venture JJK98cA0F CP3000U0G USA X CAP-JJK0A0 CAP-JJK000 CAP-JJK-140 981202
JoJo's Venture JJK98cA0F CP3000U0G USA X CAP-JJK0A0 CAP-JJK-2 CAP-JJK-160 990108
JoJo's Venture JJK98cA0F CP3000U0G USA X CAP-JJK0A0 CAP-JJK-3 CAP-JJK-161 990128
Street Fighter III 3rd Strike: Fight for the Future 1999 33S99400F CP300000G JAPAN X CAP-33S000 CAP-33S-1 CAP-33S-1 990512
Street Fighter III 3rd Strike: Fight for the Future 33S99400F CP300000G JAPAN X CAP-33S000 CAP-33S-2 CAP-33S-2 990608
Street Fighter III 3rd Strike: Fight for the Future 33S99400F CP300000G JAPAN X 990512
Street Fighter III 3rd Strike: Fight for the Future 33S99400F CP300000G JAPAN X 990608
Street Fighter III 3rd Strike: Fight for the Future 33S994A0F CP3000B0G EUROPE X CAP-33S0A0 CAP-33S-1 CAP-33S-1 990512
Street Fighter III 3rd Strike: Fight for the Future 33S994A0F CP3000B0G EUROPE X CAP-33S0A0 CAP-33S-2 CAP-33S-2 990608
Street Fighter III 3rd Strike: Fight for the Future 33S994A0F CP3000C0G ASIA* X CAP-33S0A0 CAP-33S-1 CAP-33S-1 990512
Street Fighter III 3rd Strike: Fight for the Future 33S994A0F CP3000C0G ASIA* X CAP-33S0A0 CAP-33S-2 CAP-33S-2 990608
Street Fighter III 3rd Strike: Fight for the Future 33S994A0F CP3000C0G ASIA* X 990512
Street Fighter III 3rd Strike: Fight for the Future 33S994A0F CP3000C0G ASIA* X 990608
Street Fighter III 3rd Strike: Fight for the Future 33S994A0F CP3000H0G MEXICO* ? CAP-33S0A0 CAP-33S-1 CAP-33S-1 990512
Street Fighter III 3rd Strike: Fight for the Future 33S994A0F CP3000H0G MEXICO* ? CAP-33S0A0 CAP-33S-2 CAP-33S-2 990608
Street Fighter III 3rd Strike: Fight for the Future 33S994A0F CP3000U0G USA X CAP-33S0A0 CAP-33S-1 CAP-33S-1 990512
Street Fighter III 3rd Strike: Fight for the Future 33S994A0F CP3000U0G USA X CAP-33S0A0 CAP-33S-2 CAP-33S-2 990608
JoJo no Kimyou na Bouken: Mirai e no Isan 1999 JJM99900F CP300000G JAPAN X CAP-JJM000 CAP-JJM-0 CAP-JJM-110 990913
JoJo no Kimyou na Bouken: Mirai e no Isan JJM99900F CP300000G JAPAN X CAP-JJM000 CAP-JJM-1 CAP-JJM-120 990927
JoJo no Kimyou na Bouken: Mirai e no Isan JJM99900F CP300000G JAPAN X 990913
JoJo no Kimyou na Bouken: Mirai e no Isan JJM99900F CP300000G JAPAN X 990927
JoJo's Bizarre Adventure JJM999A0F CP3000B0G EUROPE X 990913
JoJo's Bizarre Adventure JJM999A0F CP3000B0G EUROPE X 990927
* NOT DUMPED but known to exist
Each game consists of a cart and a CD having various codes needed to identify them. Carts and CDs have
both a different Part # printed on their front/top side that includes the game cart/CD code and ends
respectively with 00F/000 for all Japan releases and with A0F/0A0 for all the other ones. Therefore,
the part # can be used only to identify Japan releases and further parameters need to be introduced.
The cart is responsible for the game region that can be identified by a label with colored characters
and a code printed on the back side. The antepenultimate character of the label code and the colour of the
sticker vary by region, exactly as happens on the boot screen when the board is powered on. There are two
types of carts. Some require the CD to boot, some don't since the game is already loaded into the SIMMs.
Both types are externally identical and use the same codes, so the only way to distinguish them is to dump
the flashROMs. The game region and CD/NO CD flags are controlled by two different bytes in the flashROM.
The CD (and SIMMs too if the cart is of type NO CD) contains the game revision that can be identified
by two codes, the catalog # and the label. The catalog # is the identifying code printed in the mirror
ring on the top side close to the CD's center while the label is the code appearing on the CD icon when
it's inserted into a PC CD drive. It has been verified that the catalog # and label are the same for
some games but quite different for some others, so it's better to check both to avoid confusion. It
has also been verified that the catalog # and label (and the data on CDs) don't change between regions,
only between revisions. However, knowing one of them and comparing it with the table above will help
to understand if a new game revision has been discovered. Current CD dumps have been documented using
the catalog # as name, since the label is already included into the images used to generate CHDs.
The CP SYSTEM III comprises a main board with several custom ASICs, custom 72-pin SIMMs for program
and graphics storage (the same SIMMs are also used in some CPS2 titles), SCSI CDROM and CDROM disc,
and a plug-in security cart containing a boot flashROM, an NVRAM and a custom Capcom CPU containing
battery-backed decryption keys.
Not much is known about the actual CPU used in this system due to the extensive use of encryption and the volatile
nature of the security information. It is known that the CPU inside the security cart is the main CPU. It is known to
be a Hitachi SH-2 derivative thought to be based on a Hitachi HD6417099 SH2 variant with built-in encryption.
Tests were done by decrypting the security cart flashROM code and running it on the PCB with a dead cart with a zero
key and it didn't run so it is known that the custom CPU will not run standard (i.e. unencrypted) SH2 code.
The flashROM in the cart contains an encrypted program which is decrypted by the CPU in the cart. The CPU has built-in
decryption and the key is held in some static RAM on the CPU die and kept there by a battery. The code is executed by
the CPU to boot the system. Even though the code in the flashROM is encrypted, the cart can run it even if it is
dead/suicided because it has been discovered that the program contains a hidden security menu allowing the cart to be
loaded with the security data. This proves the cart runs the code even if the battery is dead. The special security
menu is not normally available but is likely accessed with a special key/button combination which is currently unknown.
Because the CPU in the cart is always powered by the battery, it has stealth capability that allows it to continually
monitor the situation. If the custom CPU detects any tampering (generally things such as voltage fluctuation or voltage
dropping or even removal of the cart with the power on), it immediately erases the SRAM (i.e. the decryption key)
inside the CPU which effectively kills the security cart. It is known (from decapping it) that the CPU in the security
cart contains an amount of static RAM for data storage and a SH2 core based on the Hitachi SH7010-series (SH7014)
SuperH RISC engine family of Microprocessors.
It is thought that when a cartridge dies it will set the decryption keys identical to the ones of SFIII-2nd Impact, so
removing the battery and changing the content of the flashROM (if it's not a 2nd Impact) will make it run as a normal
SFIII-2nd Impact cartridge (verified).
The main board uses the familiar Capcom SIMM modules to hold the data from the CDROM so that the life of the CD drive
is maximized. The SIMMs don't contain RAM, but instead TSOP48 surface mounted flashROMs that can be updated with
different games on bootup using a built-in software updating system.
The SIMMs that hold the program code are located in positions 1 & 2 and are 64MBit.
The SIMMs that hold the graphics and sound data are located in positions 3, 4, 5, 6 & 7 and are 128MBit.
The data in the SIMMs is not decrypted, it is merely taken directly from the CDROM and shuffled slightly then
programmed to the flashROMs. The SIMMs hold the entire contents of the CDROM.
To swap games requires the security cart for the game, it's CDROM disc and the correctly populated type and number of
SIMMs on the main board.
On first power-up after switching the cart and CD, you're presented with a screen asking if you want to re-program the
SIMMs with the new game. Pressing player 1 button 2 cancels it. Pressing player 1 button 1 allows it to proceed whereby
you wait about 25-30 minutes then the game boots up almost immediately. On subsequent power-ups, the game boots
immediately.
If the CDROM is not present in the drive on a normal bootup, a message tells you to insert the CDROM.
Then you press button 1 to continue and the game boots immediately.
Note that not all of the SIMMs are populated on the PCB for each game. Some games have more, some less, depending on
game requirements, so flash times can vary per game. See the table below for details.
|----------- Required SIMM Locations & Types -----------|
Game 1 2 3 4 5 6 7
--------------------------------------------------------------------------------------------------------------
Red Earth / Warzard 64MBit - 128MBit 128MBit 32MBit* - -
Street Fighter III: New Generation 64MBit - 128MBit 128MBit 32MBit* - -
Street Fighter III 2nd Impact: Giant Attack 64MBit 64MBit 128MBit 128MBit 128MBit - -
JoJo's Venture 64MBit 64MBit 128MBit 128MBit 32MBit* - -
Street Fighter III 3rd Strike: Fight for the Future 64MBit 64MBit 128MBit 128MBit 128MBit 128MBit -
JoJo's Bizarre Adventure 64MBit 64MBit 128MBit 128MBit 128MBit - -
Notes:
- denotes not populated
* 32MBit SIMMs have only 2 FlashROMs populated on them.
128MBit SIMMs can also be used.
No game uses a SIMM at 7
See main board diagram below for SIMM locations.
Due to the built-in upgradability of the hardware, and the higher frame-rates the hardware seems to have, it appears
Capcom had big plans for this system and possibly intended to create many games on it, as they did with CPS2.
Unfortunately for Capcom, CP SYSTEM III was an absolute flop in the arcades so those plans were cancelled. Possible
reasons include:
- the games were essentially just 2D, and already there were many 3D games coming out onto the market that interested
operators more than this.
- the cost of the system was quite expensive when compared to other games on the market.
- it is rumoured that the system was difficult to program for developers.
- these PCBs were not popular with operators because the security carts are extremely static-sensitive and most of them
failed due to the decryption information being zapped by simple handling of the PCBs or by touching the security cart
edge connector underneath the PCB while the security cart was plugged in, or by power fluctuations while flashing the
SIMMs. You will know if your cart has been zapped because on bootup, you get a screen full of garbage coloured pixels
instead of the game booting up, or just a black or single-colored screen. You should also not touch the inside of the
security cart. The PCB can detect the presence of the security cart and if it is removed on a working game, the game
will freeze immediately and it will also erase the security cart battery-backed decryption data.
PCB Layouts
-----------
CAPCOM
CP SYSTEM III
95682A-4 (older rev 95682A-3)
|----------------------------------------------------------------------|
|= J1 HM514260(2) |------------| | | | | | |
| |CAPCOM | | | | | | |
|= J2 TA8201 TC5118160 |DL-2729 PPU | | | | | | |
| |(QFP304) | | | | | | |
|--| VOL TC5118160 | | | | | | | |
| LM833N | | S S S S S |
| LM833N TC5118160 |------------| I I I I I |
| TDA1306T |--------| M M M M M |
| TC5118160 60MHz |CAPCOM | M M M M M |-|
| 42.9545MHz |DL-3329 | 7 6 5 4 3 | |
| LM385 |SSU | | | | | | | |
|J KM681002 |--------| | | | | | | |
|A KM681002 62256 |-------| | | | | | | |
|M |DL3529 | | | | | | | |
|M MC44200FU |GLL2 | | | | | | | |
|A 3.6864MHz |-------| CN6| |
| | | | |
| |--------| |-| | | | |
| |CAPCOM | | | |-------| | | | |
| TD62064 |DL-2929 | | | |CAPCOM | | | | |
| |IOU | | | |DL-3429| | | | |
| TD62064 |--------| | | |GLL1 | S S | |
|--| *HA16103FPJ | | |-------| I I |-|
| | |CN5 M M |
| | | |-------| M M |
|-| 93C46 | | |CAPCOM | 2 1 |
| | PS2501 | | |DL-2829| | | |-----||
| |CN1 | | |CCU | | | |AMD ||
| | PS2501 | | |-------| | | |33C93||
|-| |-| | | |-----||
| SW1 HM514260 | | |
|----------------------------------------------------------------------|
Notes:
TA8201 - Toshiba TA8201 18W BTL x 2-Channel Audio Power Amplifier
PS2501 - NEC PS2501 High Isolation Voltage Single Transistor Type Multi Photocoupler (DIP16)
TDA1306T - Philips TDA1306T Noise Shaping Filter DAC (SOIC24). The clock (on pin 12) measures
14.3181667MHz (42.9545/3)
MC44200FU - Motorola MC44200FU Triple 8-bit Video DAC (QFP44)
LM833N - ST Microelectronics LM833N Low Noise Audio Dual Op-Amp (DIP8)
TD62064 - Toshiba TD62064AP NPN 50V 1.5A Quad Darlington Driver (DIP16)
HA16103FPJ - Hitachi HA16103FPJ Watchdog Timer (SOIC20)
*Note this IC is not populated on the rev -4 board
93C46 - National Semiconductor NM93C46A 128bytes x8 Serial EEPROM (SOIC8)
Note this IC is covered by a plastic housing on the PCB. The chip is just a normal
(unsecured) EEPROM so why it was covered is not known.
LM385 - National Semiconductor LM385 Adjustable Micropower Voltage Reference Diode (SOIC8)
33C93 - AMD 33C93A-16 SCSI Controller (PLCC44)
KM681002 - Samsung Electronics KM681002 128k x8 SRAM (SOJ32). This is the 'Color RAM' in the test mode memory
test
62256 - 32k x8 SRAM (SOJ28). This is the 'SS RAM' in the test mode memory test and is connected to the custom
SSU chip.
HM514260(1)- Hitachi HM514260CJ7 256k x16 DRAM (SOJ40). This is the 'Work RAM' in the test mode memory test and is
connected to the custom CCU chip.
HM514260(2)- Hitachi HM514260CJ7 256k x16 DRAM (SOJ40). This is the 'Sprite RAM' in the test mode memory test
TC5118160 - Toshiba TC5118160BJ-60 or NEC 4218160-60 1M x16 DRAM (SOJ42). This is the 'Character RAM' in the
test mode memory test
SW1 - Push-button Test Switch
VOL - Master Volume Potentiometer
J1/J2 - Optional RCA Left/Right Audio Out Connectors
CN1 - 34-Pin Capcom Kick Button Harness Connector
CN5 - Security Cartridge Slot
CN6 - 4-Pin Power Connector and 50-pin SCSI Data Cable Connector
CDROM Drive is a CR504-KCM 4X SCSI drive manufactured By Panasonic / Matsushita
SIMM 1-2 - 72-Pin SIMM Connector, holds single sided SIMMs containing 4x Fujitsu 29F016A
surface mounted TSOP48 FlashROMs
SIMM 3-7 - 72-Pin SIMM Connector, holds double sided SIMMs containing 8x Fujitsu 29F016A
surface mounted TSOP48 FlashROMs
SIMM Layout -
|----------------------------------------------------|
| |
| |-------| |-------| |-------| |-------| |
| |Flash_A| |Flash_B| |Flash_C| |Flash_D| |
| |-------| |-------| |-------| |-------| |
|- |
|-------------------------/\------------------------|
Notes:
For SIMMs 1-2, Flash_A & Flash_C and regular pinout (Fujitsu 29F016A-90PFTN)
Flash_B & Flash_D are reverse pinout (Fujitsu 29F016A-90PFTR)
and are mounted upside down also so that pin1 lines up with
the normal pinout of FlashROMs A & C.
For SIMMs 3-7, the 8 FlashROMs are populated on both sides using a similar layout.
Capcom Custom ASICs -
DL-2729 PPU SD10-505 (QFP304) - Graphics chip.
DL-2829 CCU SD07-1514 (QFP208) - Probably a companion CPU or co-processor. Decapping
reveals it is manufactured by Toshiba. The 'Work RAM' is
connected to it.
DL-2929 IOU SD08-1513 (QFP208) - I/O controller, next to 3.6864MHz XTAL.
DL-3329 SSU SD04-1536 (QFP144) - Sound chip, clocked at 21.47725MHz (42.9545/2). It has 32k
SRAM connected to it, probably also 'SS' foreground layer generator.
DL-3429 GLL1 SD06-1537 (QFP144) - DMA memory/bus controller.
DL-3529 GLL2 SD11-1755 (QFP80) - ROM/SIMM bank selection chip (via 3x FCT162244 logic ICs).
Connector Pinouts
-----------------
JAMMA Connector Extra Button Connector
--------------- ----------------------
PART SIDE SOLDER SIDE TOP BOTTOM
---------------------------- --------------------------
GND 01 A GND GND 01 02 GND
GND 02 B GND +5V 03 04 +5V
+5V 03 C +5V +12V 05 06 +12V
+5V 04 D +5V 07 08
NC 05 E NC Player 2 Button 4 09 10
+12V 06 F +12V 11 12
07 H 13 14
Coin Counter 1 08 J NC Player 1 Button 4 15 16
Coin Lockout 09 K Coin Lockout Player 1 Button 5 17 18
Speaker (+) 10 L Speaker (-) Player 1 Button 6 19 20
NC 11 M NC Player 2 Button 5 21 22
Video Red 12 N Video Green Player 2 Button 6 23 24
Video Blue 13 P Video Composite Sync 25 26
Video Ground 14 R Service Switch 27 28
Test 15 S NC Volume Down 29 30 Volume UP
Coin A 16 T Coin B GND 31 32 GND
Player 1 Start 17 U Player 2 Start GND 33 34 GND
Player 1 Up 18 V Player 2 Up
Player 1 Down 19 W Player 2 Down
Player 1 Left 20 X Player 2 Left
Player 1 Right 21 Y Player 2 Right
Player 1 Button 1 22 Z Player 2 Button 1
Player 1 Button 2 23 a Player 2 Button 2
Player 1 Button 3 24 b Player 2 Button 3
NC 25 c NC
NC 26 d NC
GND 27 e GND
GND 28 f GND
Security Cartridge PCB Layout
-----------------------------
There are 4 types of CPS3 security carts. They have a label on the custom CPU that can be either A, B, C or D.
Cartridge types A/B are identical and cartridge types C/D are identical.
Type A/B have extra space on the back side to solder a 28F400 SOP44 flashROM which shares all electrical connections
with the 29F400 TSOP48 flashROM on the front side of the PCB. Either chip can be used to store the 512k cart program,
but no cart has been seen with a SOP44 flashROM populated, nor with both SOP44 and TSOP48 populated on one cart.
A and B cartridges also contain a FM1208S NVRAM which holds game settings or other per-game data. It is definitely
used. If the NVRAM data is not present when the game boots or the NVRAM is not working or inaccessible a message is
displayed 'EEPROM ERROR' and the game halts. This error can also occur if the security cart edge connector is dirty
and not contacting properly.
C and D cartridges lack the extra space to solder a SOP44 flashROM. A space is available on the back side for a FM1208S
NVRAM but it is not populated. A MACH111 CPLD is present on the back side and stamped 'CP3B1A'
Type A and Type B
-----------------
CAPCOM 95682B-3 TORNADE
|------------------------------------------------|
| BATTERY |
| |-------| |
| |CAPCOM | 29F400 |
| |DL-3229| *28F400 |
| |SCU | *FM1208S|
| 74HC00 |-------| |
| 6.25MHz 74F00 |
|---| |-| |------|
| | | |
|-----| |-----------------------------|
Notes:
74F00 - 74F00 Quad 2-Input NAND Gate (SOIC14)
74HC00 - Philips 74HC00N Quad 2-Input NAND Gate (DIP14)
29F400 - Fujitsu 29F400TA-90PFTN 512k x8 FlashROM (TSOP48)
Custom ASIC - CAPCOM DL-3229 SCU (QFP144). Decapping reveals this is a Hitachi HD6417099 SH2 variant
with built-in encryption, clocked at 6.250MHz
FM1208S - RAMTRON FM1208S 4k (512bytes x8) Nonvolatile Ferroelectric RAM (SOIC24)
28F400 - 28F400 SOP44 FlashROM (not populated)
* - These components located on the other side of the PCB
Note: The battery powers the CPU only. A small board containing some transistors/resistors is wired to the 74HC00
to switch the CPU from battery power to main power to increase the life of the battery.
Type C and Type D
-----------------
CAPCOM 95682B-4 CP SYSTEM III
|------------------------------------------------|
| BATTERY |
| |-------| |
| |CAPCOM | 29F400 |
| |DL-3229| *MACH111 |
| |SCU | *FM1208S|
| 74HC00 |-------| |
| 6.25MHz 74F00 |
|---| |-| |------|
| | | |
|-----| |-----------------------------|
Notes:
74F00 - 74F00 Quad 2-Input NAND Gate (SOIC14)
74HC00 - Philips 74HC00N Quad 2-Input NAND Gate (DIP14)
29F400 - Fujitsu 29F400TA-90PFTN 512k x8 FlashROM (TSOP48)
Custom ASIC - CAPCOM DL-3229 SCU (QFP144). Decapping reveals this is a Hitachi HD6417099 SH2 variant
with built-in encryption, clocked at 6.250MHz
FM1208S - RAMTRON FM1208S 4k (512bytes x8) Nonvolatile Ferroelectric RAM (not populated)
MACH111 - AMD MACH111 CPLD stamped 'CP3B1A' (PLCC44)
* - These components located on the other side of the PCB
Note: The battery powers the CPU only. Some transistors/resistors present on the PCB and wired to the 74HC00
switch the CPU from battery power to main power to increase the life of the battery.
Security cart resurrection info
-------------------------------
When the security cart dies the game no longer functions. The PCB can be brought back to life by doing the following
hardware modification to the security cart.....
1. Remove the custom QFP144 CPU and replace it with a standard Hitachi HD6417604 or HD6417095 SH-2 CPU
2. Remove the 29F400 TSOP48 flashROM and re-program it with the decrypted and modified main program ROM from set
'cps3boot' in MAME. A 28F400 SOP44 flashROM can be used instead and mounted to the back side of the security cart
PCB. Do not mount both SOP44 and TSOP48 flashROMs, use only one TSOP48 flashROM or one SOP44 flashROM.
3. Power on the PCB and using the built-in cart flashROM menu re-program the SIMMs for your chosen game using the CD
from set 'cps3boot' in MAME.
4. That is all. Enjoy your working PCB.
Hardware registers info
----------------------
PPU registers (read only)
0x040C0000 - 0x040C000D
Offset: Bits: Desc:
0C ---- ---- ---- -2-- Palette DMA active |
---- ---- ---- --1- Character DMA active | several parts of game code assume only 1 of these might be active at the same time
---- ---- ---- ---0 Sprite list DMA/copy active, see register 82 description
PPU registers (write only)
0x040C0000 - 0x040C00AF
Offset: Bits: Desc:
00 ---- --xx xxxx xxxx Global Scroll 0 X
02 ---- --xx xxxx xxxx Global Scroll 0 Y
04-1F Global Scrolls 1-7
20 xxxx xxxx xxxx xxxx Tilemap 0 Scroll X
22 xxxx xxxx xxxx xxxx Tilemap 0 Scroll Y
24 ---- -a98 76-- ---- Tilemap 0 ?? always 0
---- ---- ---4 3210 Tilemap 0 Width (in tiles)
26 f--- ---- ---- ---- Tilemap 0 Enable
-e-- ---- ---- ---- Tilemap 0 Line Scroll Enable
--d- ---- ---- ---- Tilemap 0 Line Zoom Enable (seems unused in games, but might be enabled in jojo dev.menu BG test)
---c ---- ---- ---- Tilemap 0 ?? set together with Zoom
---- b--- ---- ---- Tilemap 0 Flip X (not implemented, Warzard demo fights during special moves)
---- -a-- ---- ---- Tilemap 0 Flip Y (not implemented, Capcom logos background during sfiii2 flashing)
---- --98 7654 3210 Tilemap 0 ?? always 0
28 -edc ba98 ---- ---- Tilemap 0 Line Scroll and Zoom Base address (1st word is scroll, 2nd word is zoom)
---- ---- -654 3210 Tilemap 0 Tiles Base address
2A-2F unused
30-5F Tilemaps 1-3
Values: 384 495 "wide"
60 xxxx xxxx xxxx xxxx H Sync end* 42 35
62 xxxx xxxx xxxx xxxx H Blank end 111 118
64 xxxx xxxx xxxx xxxx H Screen end 495 613
66 xxxx xxxx xxxx xxxx H Total end* 454 454
68 ---- --xx xxxx xxxx H ?? Zoom Master? 0 0 +128 if flip screen, might be not zoom-related but global H scroll
6A xxxx xxxx xxxx xxxx H ?? Zoom Offset? 0 0
6C xxxx xxxx xxxx xxxx H ?? Zoom Size? 1023 1023 (511 at BIOS init)
6E xxxx xxxx xxxx xxxx H Zoom Scale 64 64
70 xxxx xxxx xxxx xxxx V Sync end 3 3
72 xxxx xxxx xxxx xxxx V Blank end 21 21
74 xxxx xxxx xxxx xxxx V Screen end 245 245
76 xxxx xxxx xxxx xxxx V Total end 262 262
78 ---- --xx xxxx xxxx V ?? Zoom Master? 0 0 might be not zoom-related but global V scroll
7A xxxx xxxx xxxx xxxx V ?? Zoom Offset? 0 0
7C xxxx xxxx xxxx xxxx V ?? Zoom Size? 1023 1023 (261 at BIOS init)
7E xxxx xxxx xxxx xxxx V Zoom Scale 64 64
80 ---- ---- ---- -210 Pixel clock 3 5 not clear how it works, which OSC is base clock, etc.
---- ---- ---4 3--- Flip screen X/Y (or Y/X)
---- ---- --5- ---- ?? always set to 1, 0 in unused 24KHz mode (pixel clock divider?)
---- ---- -6-- ---- ?? set to 0 by BIOS init, then set to 1 after video mode selection, 0 in unused 24KHz mode (pixel clock divider?)
f--- ---- ---- ---- ?? always 0, but there is code which may set it
82 ---- ---- ---- 3--0 Sprite list DMA/copy to onchip RAM ? after new list upload to sprite RAM games write here 8/9/8/9 pattern, then wait until register 0C bit 0 became 0, then write 0.
84 ---- b--- ---- ---- ?? always set to 0x0800
86 ---- ---- ---- 3210 Character RAM bank
88 ---- ---- --54 3210 Gfx flash ROM bank
8A ---- ---- ---- ---- ?? set to 0 by BIOS init, never writen later
8E ---- ---- 7-5- ---- ?? set to 0x00A0 by BIOS init after Pal/Char DMA registers, never writen later (Char/Pal DMA IRQ enable ?)
96 xxxx xxxx xxxx xxxx Character DMA Source low bits
98 ---- ---- --54 3210 Character DMA Source high bits
---- ---- -6-- ---- Character DMA Start
A0 ---- -a98 7654 3210 Palette DMA Source high bits
A2 xxxx xxxx xxxx xxxx Palette DMA Source low bits
A4 ---- ---- ---- ---0 Palette DMA Destination high bit
A6 xxxx xxxx xxxx xxxx Palette DMA Destination low bits
A8 -edc ba98 -654 3210 Palette DMA Fade low bits
AA ---- ---- -654 3210 Palette DMA Fade high bits
AC xxxx xxxx xxxx xxxx Palette DMA Lenght low bits
AE ---- ---- ---- ---0 Palette DMA Lenght high bit
---- ---- ---- --1- Palette DMA Start
All CRTC-related values is last clock/line of given area, i.e. actual sizes is +1 to value.
(*) H Total value is same for all 15KHz modes, uses fixed clock (not affected by pixel clock modifier),
probably 42.954545MHz/6 (similar to SSV) /(454+1) = 15734.25Hz /(262+1) = 59.826Hz
unused 24KHz 512x384 mode uses H Total 293 V Total 424 (42.954545MHz/6 /(293+1) = 24350.62Hz /(424+1) = 57.29Hz)
'SS' foreground tilemap layer generator (presumable located in 'SSU' chip) registers (write only?)
0x05050000 - 0x05050029 area, even bytes only.
Offset: Bits: Desc: Values: 384 495 "wide"
00 xxxx xxxx H Sync* 42 35 same as PPU
01 xxxx xxxx H Start L
02 xxxx xxxx H Start H 62 64
03 xxxx xxxx H Blank L
04 xxxx xxxx H Blank H 534 671
05 xxxx xxxx H Total L*
06 xxxx xxxx H Total H* 454 454* same as PPU
07 xxxx xxxx H Scroll L
08 xxxx xxxx H Scroll H -101 -107 +128 if flip screen
09 xxxx xxxx V Sync 3 3 same as PPU
0a xxxx xxxx V Start L
0b xxxx xxxx V Start H 21 21 same as PPU
0c xxxx xxxx V Blank L
0d xxxx xxxx V Blank H 247 247 PPU value +2
0e xxxx xxxx V Total L
0f xxxx xxxx V Total H 262 262 same as PPU
10 xxxx xxxx V Scroll L
11 xxxx xxxx V Scroll H -24 -24 +288 if flip screen
12 xxxx xxxx Palette base
13 ---- -210 Pixel clock 3 5 not clear how it works
14 ---- --10 Flip screen X/Y (or Y/X?)
(*) H Total value is same for all 15KHz modes, same as PPU.
*/
#include "emu.h"
#include "cdrom.h"
#include "cpu/sh/sh2.h"
#include "machine/intelfsh.h"
#include "machine/nvram.h"
#include "includes/cps3.h"
#include "bus/nscsi/cd.h"
#include "machine/wd33c9x.h"
#include "screen.h"
#include "speaker.h"
#include <algorithm>
#include "sfiii2.lh"
#define MASTER_CLOCK 42954500
#define DEBUG_PRINTF 0
#define DMA_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(1,2))
static constexpr u32 USER4REGION_LENGTH = 0x800000*2;
static constexpr u32 USER5REGION_LENGTH = 0x800000*10;
enum
{
CPS3_TRANSPARENCY_NONE,
CPS3_TRANSPARENCY_PEN,
CPS3_TRANSPARENCY_PEN_INDEX,
CPS3_TRANSPARENCY_PEN_INDEX_BLEND
};
inline void cps3_state::cps3_drawgfxzoom(bitmap_rgb32 &dest_bmp,const rectangle &clip,gfx_element *gfx,
u32 code,u32 color,int flipx,int flipy,int sx,int sy,
int transparency,int transparent_color,
int scalex, int scaley)
{
// u8 al;
// al = (pdrawgfx_shadow_lowpri) ? 0 : 0x80;
if (!scalex || !scaley) return;
// todo: reimplement this optimization!!
// if (scalex == 0x10000 && scaley == 0x10000)
// {
// cps3_drawgfx(dest_bmp,gfx,code,color,flipx,flipy,sx,sy,clip,transparency,transparent_color);
// return;
// }
/*
scalex and scaley are 16.16 fixed point numbers
1<<15 : shrink to 50%
1<<16 : uniform scale
1<<17 : double to 200%
*/
/* force clip to bitmap boundary */
rectangle myclip = clip;
myclip &= dest_bmp.cliprect();
/* 32-bit ONLY */
{
if (gfx)
{
// const pen_t *pal = &gfx->colortable[gfx->granularity() * (color % gfx->colors())];
u32 palbase = (gfx->granularity() * color) & 0x1ffff;
const pen_t *pal = &m_mame_colours[palbase];
const u8 *source_base = gfx->get_data(code % gfx->elements());
int sprite_screen_height = (scaley*gfx->height()+0x8000)>>16;
int sprite_screen_width = (scalex*gfx->width()+0x8000)>>16;
if (sprite_screen_width && sprite_screen_height)
{
/* compute sprite increment per screen pixel */
int dx = (gfx->width()<<16)/sprite_screen_width;
int dy = (gfx->height()<<16)/sprite_screen_height;
int ex = sx+sprite_screen_width;
int ey = sy+sprite_screen_height;
int x_index_base;
int y_index;
if (flipx)
{
x_index_base = (sprite_screen_width-1)*dx;
dx = -dx;
}
else
{
x_index_base = 0;
}
if (flipy)
{
y_index = (sprite_screen_height-1)*dy;
dy = -dy;
}
else
{
y_index = 0;
}
if (sx < myclip.left())
{ /* clip left */
int pixels = myclip.left()-sx;
sx += pixels;
x_index_base += pixels*dx;
}
if (sy < myclip.top())
{ /* clip top */
int pixels = myclip.top()-sy;
sy += pixels;
y_index += pixels*dy;
}
if (ex > myclip.right()+1)
{ /* clip right */
int pixels = ex-myclip.right()-1;
ex -= pixels;
}
if (ey > myclip.bottom()+1)
{ /* clip bottom */
int pixels = ey-myclip.bottom()-1;
ey -= pixels;
}
if (ex > sx)
{ /* skip if inner loop doesn't draw anything */
if (transparency == CPS3_TRANSPARENCY_NONE)
{
for (int y = sy; y < ey; y++)
{
const u8 *source = source_base + (y_index>>16) * gfx->rowbytes();
u32 *dest = &dest_bmp.pix32(y);
int x_index = x_index_base;
for (int x = sx; x < ex; x++)
{
dest[x] = pal[source[x_index>>16]];
x_index += dx;
}
y_index += dy;
}
}
else if (transparency == CPS3_TRANSPARENCY_PEN)
{
for (int y = sy; y < ey; y++)
{
const u8 *source = source_base + (y_index>>16) * gfx->rowbytes();
u32 *dest = &dest_bmp.pix32(y);
int x_index = x_index_base;
for (int x = sx; x < ex; x++)
{
int c = source[x_index>>16];
if (c != transparent_color) dest[x] = pal[c];
x_index += dx;
}
y_index += dy;
}
}
else if (transparency == CPS3_TRANSPARENCY_PEN_INDEX)
{
for (int y = sy; y < ey; y++)
{
const u8 *source = source_base + (y_index>>16) * gfx->rowbytes();
u32 *dest = &dest_bmp.pix32(y);
int x_index = x_index_base;
for (int x = sx; x < ex; x++)
{
int c = source[x_index>>16];
if (c != transparent_color) dest[x] = c | palbase;
x_index += dx;
}
y_index += dy;
}
}
else if (transparency == CPS3_TRANSPARENCY_PEN_INDEX_BLEND)
{
for (int y = sy; y < ey; y++)
{
const u8 *source = source_base + (y_index>>16) * gfx->rowbytes();
u32 *dest = &dest_bmp.pix32(y);
int x_index = x_index_base;
for (int x = sx; x < ex; x++)
{
int c = source[x_index>>16];
if (c != transparent_color)
{
/* blending isn't 100% understood */
// is it really ORed or bits should be replaced same as in Seta/SSV hardware ?
if (gfx->granularity() == 64)
{
// OK for sfiii2 spotlight
dest[x] |= (c & 0xf) << 13;
//if (c & 0xf0) dest[x] = machine().rand(); // ?? not used?
}
else
{
// OK for jojo intro, and warzard swords, and various shadows in sf games
dest[x] |= ((c & 1) << 15) | ((color & 1) << 16);
}
}
x_index += dx;
}
y_index += dy;
}
}
}
}
}
}
}
/* Encryption */
u16 cps3_state::rotate_left(u16 value, int n)
{
int aux = value>>(16-n);
return ((value<<n)|aux)%0x10000;
}
u16 cps3_state::rotxor(u16 val, u16 xorval)
{
u16 res = val + rotate_left(val,2);
res = rotate_left(res,4) ^ (res & (val ^ xorval));
return res;
}
u32 cps3_state::cps3_mask(u32 address, u32 key1, u32 key2)
{
// ignore all encryption
if (m_altEncryption == 2)
return 0;
address ^= key1;
u16 val = (address & 0xffff) ^ 0xffff;
val = rotxor(val, key2 & 0xffff);
val ^= (address >> 16) ^ 0xffff;
val = rotxor(val, key2 >> 16);
val ^= (address & 0xffff) ^ (key2 & 0xffff);
return val | (val << 16);
}
void cps3_state::decrypt_bios()
{
u32 *coderegion = (u32*)memregion("bios")->base();
u32 codelength = memregion("bios")->bytes();
for (int i = 0; i<codelength; i +=4)
{
u32 dword = coderegion[i/4];
u32 xormask = cps3_mask(i, m_key1, m_key2);
coderegion[i/4] = dword ^ xormask;
}
#if 0
/* Dump to file */
{
FILE *fp;
const char *gamename = machine().system().name;
char filename[256];
sprintf(filename, "%s_bios.dump", gamename);
fp=fopen(filename, "w+b");
if (fp)
{
fwrite(m_decrypted_bios, 0x080000, 1, fp);
fclose(fp);
}
}
#endif
}
void cps3_state::init_crypt(u32 key1, u32 key2, int altEncryption)
{
m_key1 = key1;
m_key2 = key2;
m_altEncryption = altEncryption;
// cache pointers to regions
if (m_user4_region)
{
m_user4 = m_user4_region->base();
}
else
{
m_user4 = auto_alloc_array(machine(), u8, USER4REGION_LENGTH);
}
if (m_user5_region)
{
m_user5 = m_user5_region->base();
}
else
{
m_user5 = auto_alloc_array(machine(), u8, USER5REGION_LENGTH);
}
m_cps3sound->set_base((s8*)m_user5);
// set strict verify
m_maincpu->sh2drc_set_options(SH2DRC_STRICT_VERIFY);
m_maincpu->sh2drc_add_fastram(0x02000000, 0x0207ffff, 0, &m_mainram[0]);
m_maincpu->sh2drc_add_fastram(0x04000000, 0x0407ffff, 0, &m_spriteram[0]);
m_maincpu->sh2drc_add_fastram(0x040C0020, 0x040C002b, 0, &m_tilemap20_regs_base[0]);
m_maincpu->sh2drc_add_fastram(0x040C0030, 0x040C003b, 0, &m_tilemap30_regs_base[0]);
decrypt_bios();
}
void cps3_state::init_redearth() { init_crypt(0x9e300ab1, 0xa175b82c, 0); }
void cps3_state::init_sfiii() { init_crypt(0xb5fe053e, 0xfc03925a, 0); }
void cps3_state::init_sfiii2() { init_crypt(0x00000000, 0x00000000, 1); } // sfiii2 runs off a 'dead' cart
void cps3_state::init_jojo() { init_crypt(0x02203ee3, 0x01301972, 0); }
void cps3_state::init_sfiii3() { init_crypt(0xa55432b4, 0x0c129981, 0); }
void cps3_state::init_jojoba() { init_crypt(0x23323ee3, 0x03021972, 0); }
void cps3_state::init_cps3boot() { init_crypt((u32)-1,(u32)-1,2); }
/* GFX decodes */
static const gfx_layout cps3_tiles16x16_layout =
{
16,16,
0x8000,
8,
{ STEP8(0,1) },
{ 3*8,2*8,1*8,0*8,7*8,6*8,5*8,4*8,
11*8,10*8,9*8,8*8,15*8,14*8,13*8,12*8 },
{ STEP16(0,8*16) },
8*256
};
static const gfx_layout cps3_tiles8x8_layout =
{
8,8,
0x200,
4,
{ STEP4(0,1) },
{ 1*4,0*4,3*4,2*4,5*4,4*4,7*4,6*4 },
{ STEP8(0,8*4) },
64*4
};
static inline u8 get_fade(int c, int f)
{
// bit 7 unknown
// bit 6 fade enable / disable
// bit 5 fade mode
// bit 4-0 fade value
if (f & 0x40) // Fading enable / disable
{
f &= 0x3f;
c = (f & 0x20) ? (c + (((0x1f - c) * (f & 0x1f)) / 0x1f)) : ((c * f) / 0x1f);
c = std::max(0, std::min(0x1f, c));
}
return c;
}
void cps3_state::set_mame_colours(int colournum, u16 data, u32 fadeval)
{
int r = (data >> 0) & 0x1f;
int g = (data >> 5) & 0x1f;
int b = (data >> 10) & 0x1f;
/* is this 100% correct? */
if (fadeval & 0x40400040)
{
//logerror("fadeval %08x\n",fadeval);
r = get_fade(r, (fadeval & 0x7f000000)>>24);
g = get_fade(g, (fadeval & 0x007f0000)>>16);
b = get_fade(b, (fadeval & 0x0000007f)>>0);
data = (data & 0x8000) | (r << 0) | (g << 5) | (b << 10);
}
colournum &= 0x1ffff;
m_colourram[colournum] = data;
m_mame_colours[colournum] = rgb_t(pal5bit(r), pal5bit(g), pal5bit(b));
if (colournum < 0x10000) m_palette->set_pen_color(colournum,m_mame_colours[colournum]/* rgb_t(r<<3,g<<3,b<<3)*/);//m_mame_colours[colournum]);
}
void cps3_state::video_start()
{
m_char_ram = make_unique_clear<u32[]>(0x800000/4);
m_mame_colours = make_unique_clear<u32[]>(0x20000);
m_ss_ram = make_unique_clear<u8[]>(0x8000);
/* create the char set (gfx will then be updated dynamically from RAM) */
m_gfxdecode->set_gfx(0, std::make_unique<gfx_element>(m_palette, cps3_tiles8x8_layout, &m_ss_ram[0x4000], 0, m_palette->entries() / 16, 0));
/* create the char set (gfx will then be updated dynamically from RAM) */
m_gfxdecode->set_gfx(1, std::make_unique<gfx_element>(m_palette, cps3_tiles16x16_layout, (u8 *)m_char_ram.get(), 0, m_palette->entries() / 64, 0));
m_gfxdecode->gfx(1)->set_granularity(64);
m_screenwidth = 384;
// the renderbuffer can be twice the size of the screen, this allows us to handle framebuffer zoom values
// between 0x00 and 0x80 (0x40 is normal, 0x80 would be 'view twice as much', 0x20 is 'view half as much')