/
arm7.cpp
2375 lines (2128 loc) · 74.2 KB
/
arm7.cpp
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// license:BSD-3-Clause
// copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz
/*****************************************************************************
*
* arm7.c
* Portable CPU Emulator for 32-bit ARM v3/4/5/6
*
* Copyright Steve Ellenoff, all rights reserved.
* Thumb, DSP, and MMU support and many bugfixes by R. Belmont and Ryan Holtz.
*
* This work is based on:
* #1) 'Atmel Corporation ARM7TDMI (Thumb) Datasheet - January 1999'
* #2) Arm 2/3/6 emulator By Bryan McPhail (bmcphail@tendril.co.uk) and Phil Stroffolino (MAME CORE 0.76)
*
*****************************************************************************/
/******************************************************************************
* Notes:
** This is a plain vanilla implementation of an ARM7 cpu which incorporates my ARM7 core.
It can be used as is, or used to demonstrate how to utilize the arm7 core to create a cpu
that uses the core, since there are numerous different mcu packages that incorporate an arm7 core.
See the notes in the arm7core.inc file itself regarding issues/limitations of the arm7 core.
**
TODO:
- Cleanups
- Fix and finish the DRC code, or remove it entirely
*****************************************************************************/
#include "emu.h"
#include "debug/debugcon.h"
#include "debugger.h"
#include "arm7.h"
#include "arm7core.h" //include arm7 core
#include "arm7help.h"
#define LOG_MMU (1U << 1)
#define LOG_DSP (1U << 2)
#define LOG_COPRO_READS (1U << 3)
#define LOG_COPRO_WRITES (1U << 4)
#define LOG_COPRO_UNKNOWN (1U << 5)
#define LOG_COPRO_RESERVED (1U << 6)
#define LOG_TLB (1U << 7)
#define LOG_TLB_MISS (1U << 8)
#define LOG_PREFETCH (1U << 9)
#define VERBOSE (0) // (LOG_COPRO_READS | LOG_COPRO_WRITES | LOG_COPRO_UNKNOWN | LOG_COPRO_RESERVED)
#include "logmacro.h"
#define PRINT_HAPYFSH2 (0)
#define PRINT_CE_KERNEL (0)
/* prototypes of coprocessor functions */
void arm7_dt_r_callback(arm_state *arm, uint32_t insn, uint32_t *prn, uint32_t (*read32)(arm_state *arm, uint32_t addr));
void arm7_dt_w_callback(arm_state *arm, uint32_t insn, uint32_t *prn, void (*write32)(arm_state *arm, uint32_t addr, uint32_t data));
// holder for the co processor Data Transfer Read & Write Callback funcs
void (*arm7_coproc_dt_r_callback)(arm_state *arm, uint32_t insn, uint32_t *prn, uint32_t (*read32)(arm_state *arm, uint32_t addr));
void (*arm7_coproc_dt_w_callback)(arm_state *arm, uint32_t insn, uint32_t *prn, void (*write32)(arm_state *arm, uint32_t addr, uint32_t data));
DEFINE_DEVICE_TYPE(ARM7, arm7_cpu_device, "arm7_le", "ARM7 (little)")
DEFINE_DEVICE_TYPE(ARM7_BE, arm7_be_cpu_device, "arm7_be", "ARM7 (big)")
DEFINE_DEVICE_TYPE(ARM710A, arm710a_cpu_device, "arm710a", "ARM710a")
DEFINE_DEVICE_TYPE(ARM710T, arm710t_cpu_device, "arm710t", "ARM710T")
DEFINE_DEVICE_TYPE(ARM7500, arm7500_cpu_device, "arm7500", "ARM7500")
DEFINE_DEVICE_TYPE(ARM9, arm9_cpu_device, "arm9", "ARM9")
DEFINE_DEVICE_TYPE(ARM920T, arm920t_cpu_device, "arm920t", "ARM920T")
DEFINE_DEVICE_TYPE(ARM946ES, arm946es_cpu_device, "arm946es", "ARM946ES")
DEFINE_DEVICE_TYPE(ARM11, arm11_cpu_device, "arm11", "ARM11")
DEFINE_DEVICE_TYPE(ARM1176JZF_S, arm1176jzf_s_cpu_device, "arm1176jzf_s", "ARM1176JZF-S")
DEFINE_DEVICE_TYPE(PXA250, pxa250_cpu_device, "pxa250", "Intel XScale PXA250")
DEFINE_DEVICE_TYPE(PXA255, pxa255_cpu_device, "pxa255", "Intel XScale PXA255")
DEFINE_DEVICE_TYPE(PXA270, pxa270_cpu_device, "pxa270", "Intel XScale PXA270")
DEFINE_DEVICE_TYPE(SA1110, sa1110_cpu_device, "sa1110", "Intel StrongARM SA-1110")
DEFINE_DEVICE_TYPE(IGS036, igs036_cpu_device, "igs036", "IGS036")
arm7_cpu_device::arm7_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm7_cpu_device(mconfig, ARM7, tag, owner, clock, 4, ARCHFLAG_T, ENDIANNESS_LITTLE)
{
}
arm7_cpu_device::arm7_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint8_t archRev, uint32_t archFlags, endianness_t endianness)
: cpu_device(mconfig, type, tag, owner, clock)
, m_program_config("program", endianness, 32, 32, 0)
, m_prefetch_word0_shift(endianness == ENDIANNESS_LITTLE ? 0 : 16)
, m_prefetch_word1_shift(endianness == ENDIANNESS_LITTLE ? 16 : 0)
, m_endian(endianness)
, m_archRev(archRev)
, m_archFlags(archFlags)
, m_vectorbase(0)
, m_pc(0)
{
std::fill(std::begin(m_r), std::end(m_r), 0);
uint32_t arch = ARM9_COPRO_ID_ARCH_V4;
if (m_archFlags & ARCHFLAG_T)
arch = ARM9_COPRO_ID_ARCH_V4T;
m_copro_id = ARM9_COPRO_ID_MFR_ARM | arch | ARM9_COPRO_ID_PART_GENERICARM7;
// TODO[RH]: Default to 3-instruction prefetch for unknown ARM variants. Derived cores should set the appropriate value in their constructors.
m_insn_prefetch_depth = 3;
std::fill_n(&m_insn_prefetch_buffer[0], 3, 0);
std::fill_n(&m_insn_prefetch_address[0], 3, 0);
std::fill_n(&m_insn_prefetch_valid[0], 3, false);
m_insn_prefetch_count = 0;
m_insn_prefetch_index = 0;
m_tlb_log = 0;
m_actual_log = 0;
}
arm7_be_cpu_device::arm7_be_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm7_cpu_device(mconfig, ARM7_BE, tag, owner, clock, 4, ARCHFLAG_T, ENDIANNESS_BIG)
{
}
arm710a_cpu_device::arm710a_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm7_cpu_device(mconfig, ARM710A, tag, owner, clock, 4, ARCHFLAG_MODE26, ENDIANNESS_LITTLE)
{
m_copro_id = ARM9_COPRO_ID_MFR_ARM
| ARM9_COPRO_ID_ARCH_V4
| ARM9_COPRO_ID_PART_ARM710;
}
arm710t_cpu_device::arm710t_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm7_cpu_device(mconfig, ARM710T, tag, owner, clock, 4, ARCHFLAG_MODE26, ENDIANNESS_LITTLE)
{
m_copro_id = ARM9_COPRO_ID_MFR_ARM
| ARM9_COPRO_ID_PART_ARM710
| 0x00800000;
}
arm7500_cpu_device::arm7500_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm7_cpu_device(mconfig, ARM7500, tag, owner, clock, 4, ARCHFLAG_MODE26, ENDIANNESS_LITTLE)
{
m_copro_id = ARM9_COPRO_ID_MFR_ARM
| ARM9_COPRO_ID_ARCH_V4
| ARM9_COPRO_ID_PART_ARM710;
}
arm9_cpu_device::arm9_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm9_cpu_device(mconfig, ARM9, tag, owner, clock, 5, ARCHFLAG_T | ARCHFLAG_E, ENDIANNESS_LITTLE)
{
}
arm9_cpu_device::arm9_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint8_t archRev, uint32_t archFlags, endianness_t endianness)
: arm7_cpu_device(mconfig, type, tag, owner, clock, archRev, archFlags, endianness)
{
uint32_t arch = ARM9_COPRO_ID_ARCH_V4;
switch (archRev)
{
case 4:
if (archFlags & ARCHFLAG_T)
arch = ARM9_COPRO_ID_ARCH_V4T;
break;
case 5:
arch = ARM9_COPRO_ID_ARCH_V5;
if (archFlags & ARCHFLAG_T)
{
arch = ARM9_COPRO_ID_ARCH_V5T;
if (archFlags & ARCHFLAG_E)
{
arch = ARM9_COPRO_ID_ARCH_V5TE;
}
}
break;
default: break;
}
m_copro_id = ARM9_COPRO_ID_MFR_ARM | arch | (0x900 << 4);
}
arm920t_cpu_device::arm920t_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm9_cpu_device(mconfig, ARM920T, tag, owner, clock, 4, ARCHFLAG_T, ENDIANNESS_LITTLE)
{
m_copro_id = ARM9_COPRO_ID_MFR_ARM
| ARM9_COPRO_ID_SPEC_REV1
| ARM9_COPRO_ID_ARCH_V4T
| ARM9_COPRO_ID_PART_ARM920
| 0; // Stepping
}
arm946es_cpu_device::arm946es_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
: arm9_cpu_device(mconfig, type, tag, owner, clock, 5, ARCHFLAG_T | ARCHFLAG_E, ENDIANNESS_LITTLE),
cp15_control(0x78)
{
m_copro_id = ARM9_COPRO_ID_MFR_ARM
| ARM9_COPRO_ID_ARCH_V5TE
| ARM9_COPRO_ID_PART_ARM946
| ARM9_COPRO_ID_STEP_ARM946_A0;
std::fill_n(&ITCM[0], 0x8000, 0);
std::fill_n(&DTCM[0], 0x4000, 0);
cp15_itcm_base = 0xffffffff;
cp15_itcm_size = 0;
cp15_itcm_end = 0;
cp15_dtcm_base = 0xffffffff;
cp15_dtcm_size = 0;
cp15_dtcm_end = 0;
cp15_itcm_reg = cp15_dtcm_reg = 0;
}
arm946es_cpu_device::arm946es_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm946es_cpu_device(mconfig, ARM946ES, tag, owner, clock)
{
}
arm11_cpu_device::arm11_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm11_cpu_device(mconfig, ARM11, tag, owner, clock, 6, ARCHFLAG_T | ARCHFLAG_E | ARCHFLAG_K, ENDIANNESS_LITTLE)
{
}
arm11_cpu_device::arm11_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint8_t archRev, uint32_t archFlags, endianness_t endianness)
: arm9_cpu_device(mconfig, type, tag, owner, clock, archRev, archFlags, endianness)
{
uint32_t arch = ARM9_COPRO_ID_ARCH_V6;
m_copro_id = ARM9_COPRO_ID_MFR_ARM | arch | (0xB00 << 4);
}
arm1176jzf_s_cpu_device::arm1176jzf_s_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm11_cpu_device(mconfig, ARM1176JZF_S, tag, owner, clock, 6, ARCHFLAG_T | ARCHFLAG_E | ARCHFLAG_K, ENDIANNESS_LITTLE)
{
m_copro_id = ARM9_COPRO_ID_MFR_ARM
| ARM9_COPRO_ID_SPEC_REV0
| ARM9_COPRO_ID_ARCH_CPUID
| ARM9_COPRO_ID_PART_ARM1176JZF_S
| ARM9_COPRO_ID_STEP_ARM1176JZF_S_R0P7;
}
// unknown configuration, but uses MPU not MMU, so closer to ARM946ES
igs036_cpu_device::igs036_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm946es_cpu_device(mconfig, IGS036, tag, owner, clock)
{
}
pxa250_cpu_device::pxa250_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm7_cpu_device(mconfig, PXA250, tag, owner, clock, 5, ARCHFLAG_T | ARCHFLAG_E | ARCHFLAG_XSCALE, ENDIANNESS_LITTLE)
{
m_copro_id = ARM9_COPRO_ID_MFR_INTEL
| ARM9_COPRO_ID_ARCH_V5TE
| ARM9_COPRO_ID_PART_PXA250
| ARM9_COPRO_ID_STEP_PXA255_A0;
}
pxa255_cpu_device::pxa255_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm7_cpu_device(mconfig, PXA255, tag, owner, clock, 5, ARCHFLAG_T | ARCHFLAG_E | ARCHFLAG_XSCALE, ENDIANNESS_LITTLE)
{
m_copro_id = ARM9_COPRO_ID_MFR_INTEL
| ARM9_COPRO_ID_ARCH_V5TE
| ARM9_COPRO_ID_PART_PXA255
| ARM9_COPRO_ID_STEP_PXA255_A0;
}
pxa270_cpu_device::pxa270_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm7_cpu_device(mconfig, PXA270, tag, owner, clock, 5, ARCHFLAG_T | ARCHFLAG_E | ARCHFLAG_XSCALE, ENDIANNESS_LITTLE)
{
m_copro_id = ARM9_COPRO_ID_MFR_INTEL
| ARM9_COPRO_ID_ARCH_V5TE
| ARM9_COPRO_ID_PART_PXA270
| ARM9_COPRO_ID_STEP_PXA255_A0;
}
sa1110_cpu_device::sa1110_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: arm7_cpu_device(mconfig, SA1110, tag, owner, clock, 4, ARCHFLAG_SA, ENDIANNESS_LITTLE)
// has StrongARM, no Thumb, no Enhanced DSP
{
m_copro_id = ARM9_COPRO_ID_MFR_INTEL
| ARM9_COPRO_ID_ARCH_V4
| ARM9_COPRO_ID_PART_SA1110
| ARM9_COPRO_ID_STEP_SA1110_B4;
}
device_memory_interface::space_config_vector arm7_cpu_device::memory_space_config() const
{
return space_config_vector {
std::make_pair(AS_PROGRAM, &m_program_config)
};
}
void arm7_cpu_device::update_reg_ptr()
{
m_reg_group = sRegisterTable[GET_MODE];
}
void arm7_cpu_device::set_cpsr(uint32_t val)
{
uint8_t old_mode = GET_CPSR & MODE_FLAG;
bool call_hook = false;
if (m_archFlags & ARCHFLAG_MODE26)
{
if ((val & 0x10) != (m_r[eCPSR] & 0x10))
{
if (val & 0x10)
{
// 26 -> 32
val = (val & 0x0FFFFF3F) | (m_r[eR15] & 0xF0000000) /* N Z C V */ | ((m_r[eR15] & 0x0C000000) >> (26 - 6)) /* I F */;
m_r[eR15] = m_r[eR15] & 0x03FFFFFC;
}
else
{
// 32 -> 26
m_r[eR15] = (m_r[eR15] & 0x03FFFFFC) /* PC */ | (val & 0xF0000000) /* N Z C V */ | ((val & 0x000000C0) << (26 - 6)) /* I F */ | (val & 0x00000003) /* M1 M0 */;
}
call_hook = true;
}
else
{
if (!(val & 0x10))
{
// mirror bits in pc
m_r[eR15] = (m_r[eR15] & 0x03FFFFFF) | (val & 0xF0000000) /* N Z C V */ | ((val & 0x000000C0) << (26 - 6)) /* I F */;
}
}
}
else
{
val |= 0x10; // force valid mode
}
if ((val & T_MASK) != (m_r[eCPSR] & T_MASK))
call_hook = true;
m_r[eCPSR] = val;
if ((GET_CPSR & MODE_FLAG) != old_mode)
{
if ((GET_CPSR & MODE_FLAG) == eARM7_MODE_USER || old_mode == eARM7_MODE_USER)
call_hook = true;
update_reg_ptr();
}
if (call_hook)
debugger_privilege_hook();
}
/**************************************************************************
* ARM TLB IMPLEMENTATION
**************************************************************************/
enum
{
TLB_COARSE = 0,
TLB_FINE
};
enum
{
FAULT_NONE = 0,
FAULT_DOMAIN,
FAULT_PERMISSION
};
// COARSE, desc_level1, vaddr
uint32_t arm7_cpu_device::get_lvl2_desc_from_page_table( uint32_t granularity, uint32_t first_desc, uint32_t vaddr )
{
uint32_t desc_lvl2 = vaddr;
switch( granularity )
{
case TLB_COARSE:
desc_lvl2 = (first_desc & COPRO_TLB_CFLD_ADDR_MASK) | ((vaddr & COPRO_TLB_VADDR_CSLTI_MASK) >> COPRO_TLB_VADDR_CSLTI_MASK_SHIFT);
if (m_tlb_log)
LOGMASKED(LOG_TLB, "%s: get_lvl2_desc_from_page_table: coarse descriptor, lvl2 address is %08x\n", machine().describe_context(), desc_lvl2);
break;
case TLB_FINE:
desc_lvl2 = (first_desc & COPRO_TLB_FPTB_ADDR_MASK) | ((vaddr & COPRO_TLB_VADDR_FSLTI_MASK) >> COPRO_TLB_VADDR_FSLTI_MASK_SHIFT);
if (m_tlb_log)
LOGMASKED(LOG_TLB, "%s: get_lvl2_desc_from_page_table: fine descriptor, lvl2 address is %08x\n", machine().describe_context(), desc_lvl2);
break;
default:
// We shouldn't be here
LOGMASKED(LOG_MMU, "ARM7: Attempting to get second-level TLB descriptor of invalid granularity (%d)\n", granularity);
break;
}
return m_program->read_dword( desc_lvl2 );
}
int arm7_cpu_device::detect_fault(int desc_lvl1, int ap, int flags)
{
switch (m_decoded_access_control[(desc_lvl1 >> 5) & 0xf])
{
case 0 : // "No access - Any access generates a domain fault"
{
return FAULT_DOMAIN;
}
case 1 : // "Client - Accesses are checked against the access permission bits in the section or page descriptor"
{
if ((ap & 3) == 3)
{
return FAULT_NONE;
}
else if (ap & 2)
{
if (((m_r[eCPSR] & MODE_FLAG) == eARM7_MODE_USER) && (flags & ARM7_TLB_WRITE))
{
return FAULT_PERMISSION;
}
}
else if (ap & 1)
{
if ((m_r[eCPSR] & MODE_FLAG) == eARM7_MODE_USER)
{
return FAULT_PERMISSION;
}
}
else
{
int s = (m_control & COPRO_CTRL_SYSTEM) ? 1 : 0;
int r = (m_control & COPRO_CTRL_ROM) ? 1 : 0;
if (s == 0)
{
if (r == 0) // "Any access generates a permission fault"
{
return FAULT_PERMISSION;
}
else // "Any write generates a permission fault"
{
if (flags & ARM7_TLB_WRITE)
{
return FAULT_PERMISSION;
}
}
}
else
{
if (r == 0) // "Only Supervisor read permitted"
{
if (((m_r[eCPSR] & MODE_FLAG) == eARM7_MODE_USER) || (flags & ARM7_TLB_WRITE))
{
return FAULT_PERMISSION;
}
}
else // "Reserved" -> assume same behaviour as S=0/R=0 case
{
return FAULT_PERMISSION;
}
}
}
}
break;
case 2 : // "Reserved - Reserved. Currently behaves like the no access mode"
{
return FAULT_DOMAIN;
}
case 3 : // "Manager - Accesses are not checked against the access permission bits so a permission fault cannot be generated"
{
return FAULT_NONE;
}
}
return FAULT_NONE;
}
arm7_cpu_device::tlb_entry *arm7_cpu_device::tlb_map_entry(const offs_t vaddr, const int flags)
{
const uint32_t section = (vaddr >> (COPRO_TLB_VADDR_FLTI_MASK_SHIFT + 2)) & 0xFFF;
tlb_entry *entries = (flags & ARM7_TLB_ABORT_D) ? m_dtlb_entries : m_itlb_entries;
const uint32_t start = section << 1;
uint32_t index = (flags & ARM7_TLB_ABORT_D) ? m_dtlb_entry_index[section] : m_itlb_entry_index[section];
bool entry_found = false;
for (uint32_t i = 0; i < 2; i++)
{
index = (index + 1) & 1;
if (!entries[start + index].valid)
{
entry_found = true;
break;
}
}
if (!entry_found)
{
index = (index + 1) & 1;
}
if (flags & ARM7_TLB_ABORT_D)
m_dtlb_entry_index[section] = index;
else
m_itlb_entry_index[section] = index;
return &entries[start + index];
}
arm7_cpu_device::tlb_entry *arm7_cpu_device::tlb_probe(const offs_t vaddr, const int flags)
{
const uint32_t section = (vaddr >> (COPRO_TLB_VADDR_FLTI_MASK_SHIFT + 2)) & 0xFFF;
tlb_entry *entries = (flags & ARM7_TLB_ABORT_D) ? m_dtlb_entries : m_itlb_entries;
const uint32_t start = section << 1;
uint32_t index = (flags & ARM7_TLB_ABORT_D) ? m_dtlb_entry_index[section] : m_itlb_entry_index[section];
if (m_tlb_log)
LOGMASKED(LOG_TLB, "%s: tlb_probe: vaddr %08x, section %02x, start %02x, index %d\n", machine().describe_context(), vaddr, section, start, index);
for (uint32_t i = 0; i < 2; i++)
{
uint32_t position = start + index;
if (entries[position].valid)
{
switch (entries[position].type)
{
case COPRO_TLB_TYPE_SECTION:
if (entries[position].table_bits == (vaddr & COPRO_TLB_STABLE_MASK))
return &entries[position];
break;
case COPRO_TLB_TYPE_LARGE:
case COPRO_TLB_TYPE_SMALL:
if (entries[position].table_bits == (vaddr & COPRO_TLB_LSTABLE_MASK))
return &entries[position];
break;
case COPRO_TLB_TYPE_TINY:
if (entries[position].table_bits == (vaddr & COPRO_TLB_TTABLE_MASK))
return &entries[position];
break;
}
}
if (m_tlb_log)
{
LOGMASKED(LOG_TLB, "%s: tlb_probe: skipped due to mismatch (valid %d, domain %02x, access %d, table_bits %08x, base_addr %08x, type %d\n",
machine().describe_context(), entries[position].valid ? 1 : 0, entries[position].domain, entries[position].access,
entries[position].table_bits, entries[position].base_addr, entries[position].type);
}
index = (index - 1) & 1;
}
return nullptr;
}
uint32_t arm7_cpu_device::get_fault_from_permissions(const uint8_t access, const uint8_t domain, const uint8_t type, int flags)
{
const uint8_t domain_bits = m_decoded_access_control[domain];
switch (domain_bits)
{
case COPRO_DOMAIN_NO_ACCESS:
if (type == COPRO_TLB_TYPE_SECTION)
return (domain << 4) | COPRO_FAULT_DOMAIN_SECTION;
return (domain << 4) | COPRO_FAULT_DOMAIN_PAGE;
case COPRO_DOMAIN_CLIENT:
{
const uint32_t mode = GET_CPSR & 0xF;
switch (access)
{
case 0: // Check System/ROM bit
{
const uint32_t sr = (COPRO_CTRL >> COPRO_CTRL_SYSTEM_SHIFT) & 3;
switch (sr)
{
case 0: // No Access
if (type == COPRO_TLB_TYPE_SECTION)
return (domain << 4) | COPRO_FAULT_PERM_SECTION;
return (domain << 4) | COPRO_FAULT_PERM_PAGE;
case 1: // No User Access, Read-Only System Access
if (mode == 0 || (flags & ARM7_TLB_WRITE))
{
if (type == COPRO_TLB_TYPE_SECTION)
return (domain << 4) | COPRO_FAULT_PERM_SECTION;
return (domain << 4) | COPRO_FAULT_PERM_PAGE;
}
return COPRO_FAULT_NONE;
case 2: // Read-Only Access
if (flags & ARM7_TLB_WRITE)
{
if (type == COPRO_TLB_TYPE_SECTION)
return (domain << 4) | COPRO_FAULT_PERM_SECTION;
return (domain << 4) | COPRO_FAULT_PERM_PAGE;
}
return COPRO_FAULT_NONE;
case 3: // Unpredictable Access
LOGMASKED(LOG_MMU, "%s: get_fault_from_permissions: Unpredictable access permissions (AP bits are 0, SR bits are 3).", machine().describe_context());
return COPRO_FAULT_NONE;
}
return COPRO_FAULT_NONE;
}
case 1: // No User Access
if (mode != 0)
return COPRO_FAULT_NONE;
if (type == COPRO_TLB_TYPE_SECTION)
return (domain << 4) | COPRO_FAULT_PERM_SECTION;
return (domain << 4) | COPRO_FAULT_PERM_PAGE;
case 2: // Read-Only User Access
if (mode != 0 || (flags & ARM7_TLB_READ))
return COPRO_FAULT_NONE;
if (type == COPRO_TLB_TYPE_SECTION)
return (domain << 4) | COPRO_FAULT_PERM_SECTION;
return (domain << 4) | COPRO_FAULT_PERM_PAGE;
case 3: // Full Access
return COPRO_FAULT_NONE;
}
return COPRO_FAULT_NONE;
}
case COPRO_DOMAIN_RESV:
LOGMASKED(LOG_MMU, "%s: get_fault_from_permissions: Domain type marked as Reserved.\n", machine().describe_context());
return COPRO_FAULT_NONE;
default:
return COPRO_FAULT_NONE;
}
}
uint32_t arm7_cpu_device::tlb_check_permissions(tlb_entry *entry, const int flags)
{
return get_fault_from_permissions(entry->access, entry->domain, entry->type, flags);
}
offs_t arm7_cpu_device::tlb_translate(tlb_entry *entry, const offs_t vaddr)
{
switch (entry->type)
{
case COPRO_TLB_TYPE_SECTION:
return entry->base_addr | (vaddr & ~COPRO_TLB_SECTION_PAGE_MASK);
case COPRO_TLB_TYPE_LARGE:
return entry->base_addr | (vaddr & ~COPRO_TLB_LARGE_PAGE_MASK);
case COPRO_TLB_TYPE_SMALL:
return entry->base_addr | (vaddr & ~COPRO_TLB_SMALL_PAGE_MASK);
case COPRO_TLB_TYPE_TINY:
return entry->base_addr | (vaddr & ~COPRO_TLB_TINY_PAGE_MASK);
default:
return 0;
}
}
bool arm7_cpu_device::page_table_finish_translation(offs_t &vaddr, const uint8_t type, const uint32_t lvl1, const uint32_t lvl2, const int flags, const uint32_t lvl1a, const uint32_t lvl2a)
{
const uint8_t domain = (uint8_t)(lvl1 >> 5) & 0xF;
uint8_t access = 0;
uint32_t table_bits = 0;
switch (type)
{
case COPRO_TLB_TYPE_SECTION:
access = (uint8_t)((lvl2 >> 10) & 3);
table_bits = vaddr & COPRO_TLB_STABLE_MASK;
break;
case COPRO_TLB_TYPE_LARGE:
{
const uint8_t subpage_shift = 4 + (uint8_t)((vaddr >> 13) & 6);
access = (uint8_t)((lvl2 >> subpage_shift) & 3);
table_bits = vaddr & COPRO_TLB_LSTABLE_MASK;
break;
}
case COPRO_TLB_TYPE_SMALL:
{
const uint8_t subpage_shift = 4 + (uint8_t)((vaddr >> 9) & 6);
access = (uint8_t)((lvl2 >> subpage_shift) & 3);
table_bits = vaddr & COPRO_TLB_LSTABLE_MASK;
break;
}
case COPRO_TLB_TYPE_TINY:
access = (uint8_t)((lvl2 >> 4) & 3);
table_bits = vaddr & COPRO_TLB_TTABLE_MASK;
break;
}
const uint32_t access_result = get_fault_from_permissions(access, domain, type, flags);
if (access_result != 0)
{
if (flags & ARM7_TLB_ABORT_P)
{
LOGMASKED(LOG_MMU, "ARM7: Page walk, Potential prefetch abort, vaddr = %08x, lvl1A = %08x, lvl1D = %08x, lvl2A = %08x, lvl2D = %08x\n", vaddr, lvl1a, lvl1, lvl2a, lvl2);
}
else if (flags & ARM7_TLB_ABORT_D)
{
LOGMASKED(LOG_MMU, "ARM7: Page walk, Data abort, vaddr = %08x, lvl1A = %08x, lvl1D = %08x, lvl2A = %08x, lvl2D = %08x\n", vaddr, lvl1a, lvl1, lvl2a, lvl2);
LOGMASKED(LOG_MMU, "access: %d, domain: %d, type: %d\n", access, domain, type);
m_faultStatus[0] = access_result;
m_faultAddress = vaddr;
m_pendingAbtD = true;
update_irq_state();
}
return false;
}
static const uint32_t s_page_masks[4] = { COPRO_TLB_SECTION_PAGE_MASK, COPRO_TLB_LARGE_PAGE_MASK, COPRO_TLB_SMALL_PAGE_MASK, COPRO_TLB_TINY_PAGE_MASK };
const uint32_t base_addr = lvl2 & s_page_masks[type];
const uint32_t paddr = base_addr | (vaddr & ~s_page_masks[type]);
if (flags)
{
tlb_entry *entry = tlb_map_entry(vaddr, flags);
entry->valid = true;
entry->domain = domain;
entry->access = access;
entry->table_bits = table_bits;
entry->base_addr = base_addr;
entry->type = type;
}
vaddr = paddr;
return true;
}
bool arm7_cpu_device::page_table_translate(offs_t &vaddr, const int flags)
{
const uint32_t lvl1_addr = m_tlb_base_mask | ((vaddr & COPRO_TLB_VADDR_FLTI_MASK) >> COPRO_TLB_VADDR_FLTI_MASK_SHIFT);
const uint32_t lvl1_desc = m_program->read_dword(lvl1_addr);
LOGMASKED(LOG_MMU, "ARM7: Translating page table entry for %08x, lvl1_addr %08x, lvl1_desc %08x\n", vaddr, lvl1_addr, lvl1_desc);
switch (lvl1_desc & 3)
{
case 0: // Unmapped
LOGMASKED(LOG_MMU, "ARM7: Translating page table entry for %08x, Unmapped, lvl1a %08x, lvl1d %08x\n", vaddr, lvl1_addr, lvl1_desc);
if (flags & ARM7_TLB_ABORT_D)
{
LOGMASKED(LOG_MMU, "ARM7: Page Table Translation failed (D), PC %08x, lvl1 unmapped, vaddr = %08x, lvl1A = %08x, lvl1D = %08x\n", m_r[eR15], vaddr, lvl1_addr, lvl1_desc);
m_faultStatus[0] = COPRO_FAULT_TRANSLATE_SECTION;
m_faultAddress = vaddr;
m_pendingAbtD = true;
update_irq_state();
}
else if (flags & ARM7_TLB_ABORT_P)
{
LOGMASKED(LOG_MMU, "ARM7: Page Table Translation failed (P), PC %08x, lvl1 unmapped, vaddr = %08x, lvl1A = %08x, lvl1D = %08x\n", m_r[eR15], vaddr, lvl1_addr, lvl1_desc);
}
return false;
case 1: // Coarse Table
{
const uint32_t lvl2_addr = (lvl1_desc & COPRO_TLB_CFLD_ADDR_MASK) | ((vaddr & COPRO_TLB_VADDR_CSLTI_MASK) >> COPRO_TLB_VADDR_CSLTI_MASK_SHIFT);
const uint32_t lvl2_desc = m_program->read_dword(lvl2_addr);
LOGMASKED(LOG_MMU, "ARM7: Translating page table entry for %08x, Coarse, lvl1a %08x, lvl1d %08x, lvl2a %08x, lvl2d %08x\n", vaddr, lvl1_addr, lvl1_desc, lvl2_addr, lvl2_desc);
switch (lvl2_desc & 3)
{
case 0: // Unmapped
if (flags & ARM7_TLB_ABORT_D)
{
LOGMASKED(LOG_MMU, "ARM7: Page Table Translation failed (D), coarse lvl2 unmapped, PC %08x, vaddr = %08x, lvl1A = %08x, lvl1D = %08x, lvl2A = %08x, lvl2D = %08x\n", m_r[eR15], vaddr, lvl1_addr, lvl1_desc, lvl2_addr, lvl2_desc);
m_faultStatus[0] = ((lvl1_desc >> 1) & 0xF0) | COPRO_FAULT_TRANSLATE_PAGE;
m_faultAddress = vaddr;
m_pendingAbtD = true;
update_irq_state();
}
else if (flags & ARM7_TLB_ABORT_P)
{
LOGMASKED(LOG_MMU, "ARM7: Page Table Translation failed (P), coarse lvl2 unmapped, PC %08x, vaddr = %08x, lvl1A = %08x, lvl1D = %08x, lvl2A = %08x, lvl2D = %08x\n", m_r[eR15], vaddr, lvl1_addr, lvl1_desc, lvl2_addr, lvl2_desc);
}
return false;
case 1: // Large Page
return page_table_finish_translation(vaddr, COPRO_TLB_TYPE_LARGE, lvl1_desc, lvl2_desc, flags, lvl1_addr, lvl2_addr);
case 2: // Small Page
return page_table_finish_translation(vaddr, COPRO_TLB_TYPE_SMALL, lvl1_desc, lvl2_desc, flags, lvl1_addr, lvl2_addr);
case 3: // Tiny Page (invalid)
LOGMASKED(LOG_MMU, "ARM7: Page Table Translation failed, tiny page present in coarse lvl2 table, PC %08x, vaddr = %08x, lvl1A = %08x, lvl1D = %08x, lvl2A = %08x, lvl2D = %08x\n", m_r[eR15], vaddr, lvl1_addr, lvl1_desc, lvl2_addr, lvl2_desc);
return false;
}
return false;
}
case 2: // Section Descriptor
LOGMASKED(LOG_MMU, "ARM7: Translating page table entry for %08x, Section, lvl1a %08x, lvl1d %08x\n", vaddr, lvl1_addr, lvl1_desc);
return page_table_finish_translation(vaddr, COPRO_TLB_TYPE_SECTION, lvl1_desc, lvl1_desc, flags, lvl1_addr, lvl1_addr);
case 3: // Fine Table
{
const uint32_t lvl2_addr = (lvl1_desc & COPRO_TLB_FPTB_ADDR_MASK) | ((vaddr & COPRO_TLB_VADDR_FSLTI_MASK) >> COPRO_TLB_VADDR_FSLTI_MASK_SHIFT);
const uint32_t lvl2_desc = m_program->read_dword(lvl2_addr);
LOGMASKED(LOG_MMU, "ARM7: Translating page table entry for %08x, Fine, lvl1a %08x, lvl1d %08x, lvl2a %08x, lvl2d %08x\n", vaddr, lvl1_addr, lvl1_desc, lvl2_addr, lvl2_desc);
switch (lvl2_desc & 3)
{
case 0: // Unmapped
if (flags & ARM7_TLB_ABORT_D)
{
LOGMASKED(LOG_MMU, "ARM7: Page Table Translation failed (D), fine lvl2 unmapped, PC %08x, vaddr = %08x, lvl1A = %08x, lvl1D = %08x, lvl2A = %08x, lvl2D = %08x\n", m_r[eR15], vaddr, lvl1_addr, lvl1_desc, lvl2_addr, lvl2_desc);
m_faultStatus[0] = ((lvl1_desc >> 1) & 0xF0) | COPRO_FAULT_TRANSLATE_PAGE;
m_faultAddress = vaddr;
m_pendingAbtD = true;
update_irq_state();
}
else if (flags & ARM7_TLB_ABORT_P)
{
LOGMASKED(LOG_MMU, "ARM7: Page Table Translation failed (P), fine lvl2 unmapped, PC %08x, vaddr = %08x, lvl1A = %08x, lvl1D = %08x, lvl2A = %08x, lvl2D = %08x\n", m_r[eR15], vaddr, lvl1_addr, lvl1_desc, lvl2_addr, lvl2_desc);
}
return false;
case 1: // Large Page
return page_table_finish_translation(vaddr, COPRO_TLB_TYPE_LARGE, lvl1_desc, lvl2_desc, flags, lvl1_addr, lvl2_addr);
case 2: // Small Page
return page_table_finish_translation(vaddr, COPRO_TLB_TYPE_SMALL, lvl1_desc, lvl2_desc, flags, lvl1_addr, lvl2_addr);
case 3: // Tiny Page
return page_table_finish_translation(vaddr, COPRO_TLB_TYPE_TINY, lvl1_desc, lvl2_desc, flags, lvl1_addr, lvl2_addr);
}
return false;
}
}
return false;
}
bool arm7_cpu_device::translate_vaddr_to_paddr(offs_t &vaddr, const int flags)
{
if (m_tlb_log)
LOGMASKED(LOG_TLB, "%s: translate_vaddr_to_paddr: vaddr %08x, flags %08x\n", machine().describe_context(), vaddr, flags);
if (vaddr < 0x2000000)
{
vaddr += m_pid_offset;
if (m_tlb_log)
LOGMASKED(LOG_TLB, "%s: translate_vaddr_to_paddr: vaddr < 32M, adding PID (%08x) = %08x\n", machine().describe_context(), m_pid_offset, vaddr);
}
tlb_entry *entry = tlb_probe(vaddr, flags);
if (entry)
{
if (m_tlb_log)
{
LOGMASKED(LOG_TLB, "%s: translate_vaddr_to_paddr: found entry (domain %02x, access %d, table_bits %08x, base_addr %08x, type %d\n",
machine().describe_context(), entry->domain, entry->access, entry->table_bits, entry->base_addr, entry->type);
}
const uint32_t access_result = tlb_check_permissions(entry, flags);
if (access_result == 0)
{
vaddr = tlb_translate(entry, vaddr);
return true;
}
else if (flags & ARM7_TLB_ABORT_P)
{
LOGMASKED(LOG_MMU, "ARM7: TLB, Potential prefetch abort, vaddr = %08x\n", vaddr);
}
else if (flags & ARM7_TLB_ABORT_D)
{
LOGMASKED(LOG_MMU, "ARM7: TLB, Data abort, vaddr = %08x\n", vaddr);
m_faultStatus[0] = access_result;
m_faultAddress = vaddr;
m_pendingAbtD = true;
update_irq_state();
}
return false;
}
else
{
if (m_tlb_log)
LOGMASKED(LOG_MMU, "No TLB entry for %08x yet, running page_table_translate\n", vaddr);
return page_table_translate(vaddr, flags);
}
}
void arm7_cpu_device::translate_insn_command(const std::vector<std::string_view> ¶ms)
{
translate_command(params, TR_FETCH);
}
void arm7_cpu_device::translate_data_command(const std::vector<std::string_view> ¶ms)
{
translate_command(params, TR_READ);
}
void arm7_cpu_device::translate_command(const std::vector<std::string_view> ¶ms, int intention)
{
uint64_t vaddr;
if (!machine().debugger().console().validate_number_parameter(params[0], vaddr)) return;
vaddr &= 0xffffffff;
offs_t paddr = (offs_t)vaddr;
address_space *space = nullptr;
bool can_translate = memory_translate(AS_PROGRAM, intention, paddr, space);
if (can_translate)
machine().debugger().console().printf("%s vaddr %08x => phys %08x\n", intention == TR_FETCH ? "instruction" : "data", (uint32_t)vaddr, paddr);
else
machine().debugger().console().printf("%s vaddr %08x => unmapped\n", intention == TR_FETCH ? "instruction" : "data");
}
bool arm7_cpu_device::memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space)
{
target_space = &space(spacenum);
/* only applies to the program address space and only does something if the MMU's enabled */
if (spacenum == AS_PROGRAM && (m_control & COPRO_CTRL_MMU_EN))
{
const int flags = intention == TR_FETCH ? ARM7_TLB_ABORT_P : ARM7_TLB_ABORT_D;
if (address < 0x2000000)
address += m_pid_offset;
tlb_entry *entry = tlb_probe(address, flags);
if (entry)
{
const uint32_t access_result = tlb_check_permissions(entry, flags);
if (access_result == 0)
{
address = tlb_translate(entry, address);
return true;
}
return false;
}
else
{
return page_table_translate(address, 0);
}
}
return true;
}
/* include the arm7 core */
#include "arm7core.hxx"
/***************************************************************************
* CPU SPECIFIC IMPLEMENTATIONS
**************************************************************************/
void arm7_cpu_device::postload()
{
update_reg_ptr();
}
void arm7_cpu_device::device_start()
{
init_ce_kernel_addrs();
m_program = &space(AS_PROGRAM);
if(m_program->endianness() == ENDIANNESS_LITTLE) {
m_program->cache(m_cachele);
m_pr32 = [this](offs_t address) -> u32 { return m_cachele.read_dword(address); };
m_prptr = [this](offs_t address) -> const void * { return m_cachele.read_ptr(address); };
} else {
m_program->cache(m_cachebe);
m_pr32 = [this](offs_t address) -> u32 { return m_cachebe.read_dword(address); };
m_prptr = [this](offs_t address) -> const void * { return m_cachebe.read_ptr(address); };
}
save_item(NAME(m_insn_prefetch_depth));
save_item(NAME(m_insn_prefetch_count));
save_item(NAME(m_insn_prefetch_index));
save_item(NAME(m_insn_prefetch_buffer));
save_item(NAME(m_insn_prefetch_address));
save_item(NAME(m_insn_prefetch_valid));
save_item(NAME(m_tlb_log));
save_item(NAME(m_actual_log));
save_item(NAME(m_r));
save_item(NAME(m_pendingIrq));
save_item(NAME(m_pendingFiq));
save_item(NAME(m_pendingAbtD));
save_item(NAME(m_pendingAbtP));
save_item(NAME(m_pendingUnd));
save_item(NAME(m_pendingSwi));
save_item(NAME(m_pending_interrupt));
save_item(NAME(m_control));
save_item(NAME(m_tlbBase));
save_item(NAME(m_tlb_base_mask));
save_item(NAME(m_faultStatus));
save_item(NAME(m_faultAddress));
save_item(NAME(m_fcsePID));
save_item(NAME(m_pid_offset));
save_item(NAME(m_domainAccessControl));
save_item(NAME(m_decoded_access_control));
save_item(STRUCT_MEMBER(m_dtlb_entries, valid));
save_item(STRUCT_MEMBER(m_dtlb_entries, domain));
save_item(STRUCT_MEMBER(m_dtlb_entries, access));
save_item(STRUCT_MEMBER(m_dtlb_entries, table_bits));
save_item(STRUCT_MEMBER(m_dtlb_entries, base_addr));
save_item(STRUCT_MEMBER(m_dtlb_entries, type));
save_item(STRUCT_MEMBER(m_itlb_entries, valid));
save_item(STRUCT_MEMBER(m_itlb_entries, domain));
save_item(STRUCT_MEMBER(m_itlb_entries, access));
save_item(STRUCT_MEMBER(m_itlb_entries, table_bits));
save_item(STRUCT_MEMBER(m_itlb_entries, base_addr));
save_item(STRUCT_MEMBER(m_itlb_entries, type));
save_item(NAME(m_dtlb_entry_index));
save_item(NAME(m_itlb_entry_index));
machine().save().register_postload(save_prepost_delegate(FUNC(arm7_cpu_device::postload), this));
set_icountptr(m_icount);
state_add( ARM7_PC, "PC", m_pc).callexport().formatstr("%08X");
state_add(STATE_GENPC, "GENPC", m_pc).callexport().noshow();
state_add(STATE_GENPCBASE, "CURPC", m_pc).callexport().noshow();
/* registers shared by all operating modes */
state_add( ARM7_R0, "R0", m_r[ 0]).formatstr("%08X");
state_add( ARM7_R1, "R1", m_r[ 1]).formatstr("%08X");
state_add( ARM7_R2, "R2", m_r[ 2]).formatstr("%08X");
state_add( ARM7_R3, "R3", m_r[ 3]).formatstr("%08X");