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ddragon.cpp
2241 lines (1781 loc) · 107 KB
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ddragon.cpp
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// license:BSD-3-Clause
// copyright-holders:Philip Bennett,Carlos A. Lozano, Rob Rosenbrock, Phil Stroffolino, Ernesto Corvi, David Haywood, R. Belmont
/***************************************************************************
Double Dragon (c) 1987 Technos Japan
Double Dragon II (c) 1988 Technos Japan
Driver by Carlos A. Lozano, Rob Rosenbrock, Phil Stroffolino, Ernesto Corvi
Toffy / Super Toffy added by David Haywood
Thanks to Bryan McPhail for spotting the Toffy program rom encryption
Toffy / Super Toffy sound hooked up by R. Belmont.
Modifications by Phil Bennett Sep 2013:
Cleanups based on Double Dragon schematics.
Fixed sub CPU interrupt handling and common RAM access.
Removed now-unnecessary workarounds.
Modifications by Bryan McPhail, June-November 2003:
Correct video & interrupt timing derived from Xain schematics and confirmed on real DD board.
Corrected interrupt handling, especially to MCU (but one semi-hack remains).
TStrike now boots but sprites don't appear (I had them working at one point, can't remember what broke them again).
Dangerous Dungeons fixed.
World version of Double Dragon added (actually same roms as the bootleg, but confirmed from real board)
Removed stereo audio flag (still on Toffy - does it have it?)
todo:
banking in Toffy / Super toffy
-- Read Me --
Super Toffy - Unico 1994
Main cpu: MC6809EP
Sound cpu: MC6809P
Sound: YM2151
Clocks: 12 MHz, 3.579MHz
Graphics custom: MDE-2001
-- --
Does this make Super Toffy the sequel to a rip-off / bootleg of a
conversion kit which could be applied to a bootleg double dragon :-p?
2008-08
Dip locations verified with manual for ddragon & ddragon2
***************************************************************************/
#include "emu.h"
#include "ddragon.h"
#include "cpu/m6809/hd6309.h"
#include "cpu/m6800/m6801.h"
#include "cpu/m6809/m6809.h"
#include "cpu/z80/z80.h"
#include "sound/okim6295.h"
#include "sound/ymopm.h"
#include "sound/ymopn.h"
#include "speaker.h"
#define MAIN_CLOCK XTAL(12'000'000)
#define SOUND_CLOCK XTAL(3'579'545)
#define MCU_CLOCK MAIN_CLOCK / 3
#define PIXEL_CLOCK MAIN_CLOCK / 2
/*************************************
*
* Video timing
*
*************************************/
/*
Vertical timing counts as follows:
08,09,0A,0B,...,FC,FD,FE,FF,E8,E9,EA,EB,...,FC,FD,FE,FF,
08,09,....
Thus, it counts from 08 to FF, then resets to E8 and counts to FF again.
This gives (256 - 8) + (256 - 232) = 248 + 24 = 272 total scanlines.
VBLK is signalled starting when the counter hits F8, and continues through
the reset to E8 and through until the next reset to 08 again.
Since MAME's video timing is 0-based, we need to convert this.
*/
int ddragon_state::scanline_to_vcount( int scanline )
{
int vcount = scanline + 8;
if (vcount < 0x100)
return vcount;
else
return (vcount - 0x18) | 0x100;
}
TIMER_DEVICE_CALLBACK_MEMBER(ddragon_state::ddragon_scanline)
{
int scanline = param;
int screen_height = m_screen->height();
int vcount_old = scanline_to_vcount((scanline == 0) ? screen_height - 1 : scanline - 1);
int vcount = scanline_to_vcount(scanline);
/* update to the current point */
if (scanline > 0)
m_screen->update_partial(scanline - 1);
/* on the rising edge of VBLK (vcount == F8), signal an NMI */
if (vcount == 0xf8)
m_maincpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
/* set 1ms signal on rising edge of vcount & 8 */
if (!(vcount_old & 8) && (vcount & 8))
m_maincpu->set_input_line(M6809_FIRQ_LINE, ASSERT_LINE);
}
/*************************************
*
* System setup and initialization
*
*************************************/
void ddragon_state::machine_start()
{
/* configure banks */
if (m_mainbank)
m_mainbank->configure_entries(0, 8, memregion("maincpu")->base() + 0x10000, 0x4000);
/* register for save states */
save_item(NAME(m_scrollx_hi));
save_item(NAME(m_scrolly_hi));
save_item(NAME(m_adpcm_pos));
save_item(NAME(m_adpcm_end));
save_item(NAME(m_adpcm_idle));
save_item(NAME(m_adpcm_data));
save_item(NAME(m_ddragon_sub_port));
}
void ddragon_state::machine_reset()
{
m_scrollx_hi = 0;
m_scrolly_hi = 0;
m_ddragon_sub_port = 0;
m_adpcm_pos[0] = m_adpcm_pos[1] = 0;
m_adpcm_end[0] = m_adpcm_end[1] = 0;
m_adpcm_idle[0] = m_adpcm_idle[1] = true;
m_adpcm_data[0] = m_adpcm_data[1] = -1;
}
/*************************************
*
* Bank switching
*
*************************************/
void ddragon_state::ddragon_bankswitch_w(uint8_t data)
{
/*
76543210
.......x X-scroll D9 (H9BT)
......x. Y-scroll D9 (V9BT)
.....x.. /Screen flip (*1P/2P)
....x... /Sub CPU reset (*RESET)
...x.... /Sub CPU halt (*HALT)
xxx..... ROM bank (*BANK)
*/
m_scrollx_hi = data & 0x01;
m_scrolly_hi = (data & 0x02) >> 1;
flip_screen_set(~data & 0x04);
m_subcpu->set_input_line(INPUT_LINE_RESET, data & 0x08 ? CLEAR_LINE : ASSERT_LINE);
m_subcpu->set_input_line(INPUT_LINE_HALT, data & 0x10 ? ASSERT_LINE : CLEAR_LINE);
m_mainbank->set_entry((data & 0xe0) >> 5);
}
void toffy_state::toffy_bankswitch_w(uint8_t data)
{
m_scrollx_hi = data & 0x01;
m_scrolly_hi = (data & 0x02) >> 1;
// flip_screen_set(machine(), ~data & 0x04);
/* I don't know ... */
m_mainbank->set_entry((data & 0x20) >> 5);
}
uint8_t darktowr_state::darktowr_mcu_bank_r(offs_t offset)
{
// logerror("BankRead %05x %08x\n",m_maincpu->pc(),offset);
/* Horrible hack - the alternate TStrike set is mismatched against the MCU,
so just hack around the protection here. (The hacks are 'right' as I have
the original source code & notes to this version of TStrike to examine).
*/
if (!strcmp(machine().system().name, "tstrike"))
{
/* Static protection checks at boot-up */
if (m_maincpu->pc() == 0x9ace)
return 0;
if (m_maincpu->pc() == 0x9ae4)
return 0x63;
/* Just return whatever the code is expecting */
return m_rambase[0xbe1];
}
if (offset == 0x1401 || offset == 1)
return m_mcu_port_a_out;
logerror("Unmapped mcu bank read %04x\n",offset);
return 0xff;
}
void darktowr_state::darktowr_mcu_bank_w(offs_t offset, uint8_t data)
{
logerror("BankWrite %05x %08x %08x\n", m_maincpu->pc(), offset, data);
if (offset == 0x1400 || offset == 0)
{
uint8_t const value(bitswap<8>(data, 0, 1, 2, 3, 4, 5, 6, 7));
m_mcu->pb_w(value);
logerror("MCU PORT 1 -> %04x (from %04x)\n", value, data);
}
}
void darktowr_state::darktowr_bankswitch_w(uint8_t data)
{
m_scrollx_hi = (data & 0x01);
m_scrolly_hi = ((data & 0x02) >> 1);
// flip_screen_set(machine(), ~data & 0x04);
m_subcpu->set_input_line(INPUT_LINE_RESET, data & 0x08 ? CLEAR_LINE : ASSERT_LINE);
m_subcpu->set_input_line(INPUT_LINE_HALT, data & 0x10 ? ASSERT_LINE : CLEAR_LINE);
m_darktowr_bank->set_bank((data & 0xe0) >> 5);
}
/*************************************
*
* Interrupt control
*
*************************************/
void ddragon_state::ddragon_interrupt_ack(offs_t offset, uint8_t data)
{
switch (offset)
{
case 0: /* 380b - NMI ack */
m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
break;
case 1: /* 380c - FIRQ ack */
m_maincpu->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
break;
case 2: /* 380d - IRQ ack */
m_maincpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
break;
case 3: /* 380e - SND IRQ and latch */
m_soundlatch->write(data);
break;
case 4: /* 380f - MCU IRQ */
if (m_subcpu)
m_subcpu->set_input_line(m_sprite_irq, ASSERT_LINE);
break;
}
}
uint8_t ddragon_state::ddragon_interrupt_r(offs_t offset)
{
ddragon_interrupt_ack(offset, 0xff);
return 0xff;
}
void ddragon_state::ddragon_interrupt_w(offs_t offset, uint8_t data)
{
ddragon_interrupt_ack(offset, data);
}
void ddragon_state::ddragon2_sub_irq_ack_w(uint8_t data)
{
m_subcpu->set_input_line(m_sprite_irq, CLEAR_LINE);
}
void ddragon_state::ddragon2_sub_irq_w(uint8_t data)
{
m_maincpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
}
void ddragon_state::ddragonba_port_w(uint8_t data)
{
if ((data & 0x8) == 0)
m_subcpu->set_input_line(m_sprite_irq, CLEAR_LINE);
if (!(m_ddragon_sub_port & 0x10) && (data & 0x10))
m_maincpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
m_ddragon_sub_port = data;
}
/*************************************
*
* MCU handlers
*
*************************************/
int ddragon_state::subcpu_bus_free_r()
{
// Corresponds to BA (Bus Available) on the HD63701
if (m_subcpu)
return m_subcpu->suspended(SUSPEND_REASON_RESET | SUSPEND_REASON_HALT);
else
return 0;
}
void darktowr_state::mcu_port_a_w(offs_t offset, uint8_t data)
{
logerror("%s: McuWrite %08x %08x\n", machine().describe_context(), offset, data);
m_mcu_port_a_out = data;
}
void ddragon_state::sub_port6_w(uint8_t data)
{
// Port 6
if ((data & 0x1) == 0)
m_subcpu->set_input_line(m_sprite_irq, CLEAR_LINE);
if (!(m_ddragon_sub_port & 0x2) && (data & 0x2))
m_maincpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
m_ddragon_sub_port = data;
}
/*************************************
*
* Sprite RAM hacks
*
*************************************/
uint8_t ddragon_state::ddragon_comram_r(offs_t offset)
{
// Access to shared RAM is prevented when the sub CPU is active
if (!m_subcpu->suspended(SUSPEND_REASON_RESET | SUSPEND_REASON_HALT))
return 0xff;
return m_comram[offset];
}
void ddragon_state::ddragon_comram_w(offs_t offset, uint8_t data)
{
if (!m_subcpu->suspended(SUSPEND_REASON_RESET | SUSPEND_REASON_HALT))
return;
m_comram[offset] = data;
}
/*************************************
*
* ADPCM sound
*
*************************************/
void ddragon_state::dd_adpcm_w(offs_t offset, uint8_t data)
{
int chip = offset & 1;
switch (offset >> 1)
{
case 3:
m_adpcm_idle[chip] = true;
m_adpcm[chip]->reset_w(1);
break;
case 2:
m_adpcm_pos[chip] = (data & 0x7f) << 9;
break;
case 1:
m_adpcm_end[chip] = (data & 0x7f) << 9;
break;
case 0:
m_adpcm_idle[chip] = false;
m_adpcm[chip]->reset_w(0);
break;
}
}
void ddragon_state::dd_adpcm_int( int chip )
{
if (m_adpcm_pos[chip] >= m_adpcm_end[chip] || m_adpcm_pos[chip] >= m_adpcm_rom[chip].length())
{
m_adpcm_idle[chip] = true;
m_adpcm[chip]->reset_w(1);
}
else if (m_adpcm_data[chip] != -1)
{
m_adpcm[chip]->data_w(m_adpcm_data[chip] & 0x0f);
m_adpcm_data[chip] = -1;
}
else
{
m_adpcm_data[chip] = m_adpcm_rom[chip][m_adpcm_pos[chip]++];
m_adpcm[chip]->data_w(m_adpcm_data[chip] >> 4);
}
}
void ddragon_state::dd_adpcm_int_1(int state)
{
dd_adpcm_int(0);
}
void ddragon_state::dd_adpcm_int_2(int state)
{
dd_adpcm_int(1);
}
uint8_t ddragon_state::dd_adpcm_status_r()
{
return (m_adpcm_idle[0] ? 1 : 0) | (m_adpcm_idle[1] ? 2 : 0);
}
/*************************************
*
* Main CPU memory maps
*
*************************************/
void ddragon_state::ddragon_base_map(address_map &map)
{
map(0x0000, 0x0fff).ram().share("rambase");
map(0x1000, 0x11ff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
map(0x1200, 0x13ff).ram().w(m_palette, FUNC(palette_device::write8_ext)).share("palette_ext");
map(0x1800, 0x1fff).ram().w(FUNC(ddragon_state::ddragon_fgvideoram_w)).share("fgvideoram");
map(0x2000, 0x21ff).rw(FUNC(ddragon_state::ddragon_comram_r), FUNC(ddragon_state::ddragon_comram_w)).mirror(0x0600);
map(0x2800, 0x2fff).ram().share("spriteram");
map(0x3000, 0x37ff).ram().w(FUNC(ddragon_state::ddragon_bgvideoram_w)).share("bgvideoram");
map(0x3800, 0x3800).portr("P1");
map(0x3801, 0x3801).portr("P2");
map(0x3802, 0x3802).portr("EXTRA");
map(0x3803, 0x3803).portr("DSW0");
map(0x3804, 0x3804).portr("DSW1");
map(0x3809, 0x3809).writeonly().share("scrollx_lo");
map(0x380a, 0x380a).writeonly().share("scrolly_lo");
map(0x380b, 0x380f).rw(FUNC(ddragon_state::ddragon_interrupt_r), FUNC(ddragon_state::ddragon_interrupt_w));
map(0x8000, 0xffff).rom();
}
void ddragon_state::ddragon_map(address_map &map)
{
ddragon_base_map(map);
map(0x3808, 0x3808).w(FUNC(ddragon_state::ddragon_bankswitch_w));
map(0x4000, 0x7fff).bankr("mainbank");
}
void toffy_state::toffy_map(address_map &map)
{
ddragon_base_map(map);
map(0x3808, 0x3808).w(FUNC(toffy_state::toffy_bankswitch_w));
map(0x4000, 0x7fff).bankr("mainbank");
}
void darktowr_state::darktowr_map(address_map &map)
{
ddragon_base_map(map);
map(0x3808, 0x3808).w(FUNC(darktowr_state::darktowr_bankswitch_w));
map(0x4000, 0x7fff).m(m_darktowr_bank, FUNC(address_map_bank_device::amap8));
}
void darktowr_state::darktowr_banked_map(address_map &map)
{
map(0x00000, 0x0ffff).rom().region("maincpu", 0x10000);
map(0x10000, 0x13fff).rw(FUNC(darktowr_state::darktowr_mcu_bank_r), FUNC(darktowr_state::darktowr_mcu_bank_w));
map(0x14000, 0x1ffff).rom().region("maincpu", 0x24000); // TODO : ROM? empty at most of darktowr_state games
}
void ddragon_state::dd2_map(address_map &map)
{
map(0x0000, 0x17ff).ram();
map(0x1800, 0x1fff).ram().w(FUNC(ddragon_state::ddragon_fgvideoram_w)).share("fgvideoram");
map(0x2000, 0x21ff).rw(FUNC(ddragon_state::ddragon_comram_r), FUNC(ddragon_state::ddragon_comram_w)).mirror(0x0600);
map(0x2800, 0x2fff).ram().share("spriteram");
map(0x3000, 0x37ff).ram().w(FUNC(ddragon_state::ddragon_bgvideoram_w)).share("bgvideoram");
map(0x3800, 0x3800).portr("P1");
map(0x3801, 0x3801).portr("P2");
map(0x3802, 0x3802).portr("EXTRA");
map(0x3803, 0x3803).portr("DSW0");
map(0x3804, 0x3804).portr("DSW1");
map(0x3808, 0x3808).w(FUNC(ddragon_state::ddragon_bankswitch_w));
map(0x3809, 0x3809).writeonly().share("scrollx_lo");
map(0x380a, 0x380a).writeonly().share("scrolly_lo");
map(0x380b, 0x380f).rw(FUNC(ddragon_state::ddragon_interrupt_r), FUNC(ddragon_state::ddragon_interrupt_w));
map(0x3c00, 0x3dff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
map(0x3e00, 0x3fff).ram().w(m_palette, FUNC(palette_device::write8_ext)).share("palette_ext");
map(0x4000, 0x7fff).bankr("mainbank");
map(0x8000, 0xffff).rom();
}
/*************************************
*
* Sub CPU memory maps
*
*************************************/
void ddragon_state::sub_map(address_map &map)
{
map(0x8000, 0x81ff).ram().share("comram");
}
void ddragon_state::sub_6309_map(address_map &map)
{
map(0x0005, 0x0005).nopw();
map(0x0016, 0x0016).nopw();
map(0x0017, 0x0017).w(FUNC(ddragon_state::sub_port6_w));
map(0x0020, 0x0fff).ram();
map(0x8000, 0x81ff).ram().share("comram");
map(0xc000, 0xffff).rom();
}
void ddragon_state::sub_6809_map(address_map &map) // TODO: everything
{
map(0x8000, 0xffff).rom().region("sub", 0);
}
void ddragon_state::ddragonba_sub_map(address_map &map)
{
map(0x0100, 0x0fff).ram();
map(0x8000, 0x81ff).ram().share("comram");
map(0xc000, 0xffff).rom();
}
void ddragon_state::dd2_sub_map(address_map &map)
{
map(0x0000, 0xbfff).rom();
map(0xc000, 0xc3ff).ram().share("comram");
map(0xd000, 0xd000).w(FUNC(ddragon_state::ddragon2_sub_irq_ack_w));
map(0xe000, 0xe000).w(FUNC(ddragon_state::ddragon2_sub_irq_w));
}
/*************************************
*
* Sound CPU memory maps
*
*************************************/
void ddragon_state::sound_map(address_map &map)
{
map(0x0000, 0x0fff).ram();
map(0x1000, 0x1000).r(m_soundlatch, FUNC(generic_latch_8_device::read));
map(0x1800, 0x1800).r(FUNC(ddragon_state::dd_adpcm_status_r));
map(0x2800, 0x2801).rw("fmsnd", FUNC(ym2151_device::read), FUNC(ym2151_device::write));
map(0x3800, 0x3807).w(FUNC(ddragon_state::dd_adpcm_w));
map(0x8000, 0xffff).rom();
}
void ddragon_state::ddragon6809_sound_map(address_map &map) // TODO: everything
{
// 2x YM2203, 2xMSM5205
map(0x8000, 0xffff).rom();
}
void ddragon_state::dd2_sound_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0x87ff).ram();
map(0x8800, 0x8801).rw("fmsnd", FUNC(ym2151_device::read), FUNC(ym2151_device::write));
map(0x9800, 0x9800).rw("oki", FUNC(okim6295_device::read), FUNC(okim6295_device::write));
map(0xa000, 0xa000).r(m_soundlatch, FUNC(generic_latch_8_device::read));
}
/*************************************
*
* Input ports
*
*************************************/
static INPUT_PORTS_START( ddragon )
PORT_START("P1")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
PORT_START("P2")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_START("DSW0")
PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:1,2,3")
PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x01, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x07, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x06, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x05, DEF_STR( 1C_3C ) )
PORT_DIPSETTING( 0x04, DEF_STR( 1C_4C ) )
PORT_DIPSETTING( 0x03, DEF_STR( 1C_5C ) )
PORT_DIPNAME( 0x38, 0x38, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:4,5,6")
PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x38, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x30, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x28, DEF_STR( 1C_3C ) )
PORT_DIPSETTING( 0x20, DEF_STR( 1C_4C ) )
PORT_DIPSETTING( 0x18, DEF_STR( 1C_5C ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW1:7")
PORT_DIPSETTING( 0x40, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW1")
PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
PORT_DIPSETTING( 0x01, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x03, DEF_STR( Medium ) )
PORT_DIPSETTING( 0x02, DEF_STR( Hard ) )
PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:3")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x04, DEF_STR( On ) )
PORT_DIPUNUSED_DIPLOC( 0x08, IP_ACTIVE_LOW, "SW2:4" )
PORT_DIPNAME( 0x30, 0x30, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:5,6")
PORT_DIPSETTING( 0x10, "20k" )
PORT_DIPSETTING( 0x00, "40k" )
PORT_DIPSETTING( 0x30, "30k and every 60k" )
PORT_DIPSETTING( 0x20, "40k and every 80k" )
PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:7,8")
PORT_DIPSETTING( 0xc0, "2" )
PORT_DIPSETTING( 0x80, "3" )
PORT_DIPSETTING( 0x40, "4" )
PORT_DIPSETTING( 0x00, "Infinite (Cheat)")
PORT_START("EXTRA")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON3 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_VBLANK("screen")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_READ_LINE_MEMBER(ddragon_state, subcpu_bus_free_r)
PORT_BIT( 0xe0, IP_ACTIVE_HIGH, IPT_UNUSED )
INPUT_PORTS_END
static INPUT_PORTS_START( ddragon2 )
PORT_INCLUDE(ddragon)
PORT_MODIFY("DSW1")
PORT_DIPNAME( 0x03, 0x02, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
PORT_DIPSETTING( 0x01, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x03, DEF_STR( Medium ) )
PORT_DIPSETTING( 0x02, DEF_STR( Hard ) )
PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
PORT_DIPNAME( 0x08, 0x00, "Hurricane Kick" ) PORT_DIPLOCATION("SW2:4")
PORT_DIPSETTING( 0x00, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x08, DEF_STR( Normal ) )
PORT_DIPNAME( 0x30, 0x10, "Timer" ) PORT_DIPLOCATION("SW2:5,6")
PORT_DIPSETTING( 0x00, "Very Fast" )
PORT_DIPSETTING( 0x10, "Fast" )
PORT_DIPSETTING( 0x30, "Normal" )
PORT_DIPSETTING( 0x20, "Slow" )
PORT_DIPNAME( 0xc0, 0x80, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:7,8")
PORT_DIPSETTING( 0xc0, "1" )
PORT_DIPSETTING( 0x80, "2" )
PORT_DIPSETTING( 0x40, "3" )
PORT_DIPSETTING( 0x00, "4" )
INPUT_PORTS_END
static INPUT_PORTS_START( tstrike )
PORT_INCLUDE(ddragon)
PORT_MODIFY("DSW1")
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Difficulty ) )
PORT_DIPSETTING( 0x0c, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x08, DEF_STR( Normal ) )
PORT_DIPSETTING( 0x04, DEF_STR( Hard ) )
PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )
PORT_DIPSETTING( 0x30, "1" )
PORT_DIPSETTING( 0x20, "2" )
PORT_DIPSETTING( 0x10, "3" )
PORT_DIPSETTING( 0x00, "4" )
PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Bonus_Life ) )
PORT_DIPSETTING( 0xc0, "100k and 200k" )
PORT_DIPSETTING( 0x80, "200k and 300k" )
PORT_DIPSETTING( 0x40, "300k and 400k" )
PORT_DIPSETTING( 0x00, "400k and 500k" )
INPUT_PORTS_END
static INPUT_PORTS_START( ddungeon )
PORT_INCLUDE(ddragon)
// Dangerous Dungeons installation guide recommends 4-way joystick "for maximum profits"
PORT_MODIFY("P1")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY
PORT_MODIFY("P2")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(2)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_PLAYER(2)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(2)
PORT_MODIFY("DSW0")
PORT_DIPNAME( 0x0f, 0x00, DEF_STR( Coin_A ) )
PORT_DIPSETTING( 0x03, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x07, DEF_STR( 4C_2C ) )
PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x06, DEF_STR( 3C_2C ) )
PORT_DIPSETTING( 0x0b, DEF_STR( 4C_3C ) )
PORT_DIPSETTING( 0x0f, DEF_STR( 4C_4C ) )
PORT_DIPSETTING( 0x0a, DEF_STR( 3C_3C ) )
PORT_DIPSETTING( 0x05, DEF_STR( 2C_2C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x0e, DEF_STR( 3C_4C ) )
PORT_DIPSETTING( 0x09, DEF_STR( 2C_3C ) )
PORT_DIPSETTING( 0x0d, DEF_STR( 2C_4C ) )
PORT_DIPSETTING( 0x04, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 1C_3C ) )
PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) )
PORT_DIPNAME( 0xf0, 0x00, DEF_STR( Coin_B ) )
PORT_DIPSETTING( 0x30, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x20, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x70, DEF_STR( 4C_2C ) )
PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x60, DEF_STR( 3C_2C ) )
PORT_DIPSETTING( 0xb0, DEF_STR( 4C_3C ) )
PORT_DIPSETTING( 0xf0, DEF_STR( 4C_4C ) )
PORT_DIPSETTING( 0xa0, DEF_STR( 3C_3C ) )
PORT_DIPSETTING( 0x50, DEF_STR( 2C_2C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0xe0, DEF_STR( 3C_4C ) )
PORT_DIPSETTING( 0x90, DEF_STR( 2C_3C ) )
PORT_DIPSETTING( 0xd0, DEF_STR( 2C_4C ) )
PORT_DIPSETTING( 0x40, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x80, DEF_STR( 1C_3C ) )
PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
PORT_MODIFY("DSW1")
PORT_DIPNAME( 0x03, 0x01, DEF_STR( Lives ) )
PORT_DIPSETTING( 0x00, "1" )
PORT_DIPSETTING( 0x01, "2" )
PORT_DIPSETTING( 0x02, "3" )
PORT_DIPSETTING( 0x03, "4" )
PORT_DIPUNUSED( 0x04, IP_ACTIVE_LOW )
PORT_DIPUNUSED( 0x08, IP_ACTIVE_LOW )
PORT_DIPNAME( 0xf0, 0x90, DEF_STR( Difficulty ) )
PORT_DIPSETTING( 0xf0, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x90, DEF_STR( Medium ) )
PORT_DIPSETTING( 0x70, DEF_STR( Hard ) )
PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
INPUT_PORTS_END
static INPUT_PORTS_START( darktowr )
PORT_INCLUDE(ddungeon)
PORT_MODIFY("DSW1")
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
static INPUT_PORTS_START( toffy )
PORT_INCLUDE(ddungeon)
PORT_MODIFY("DSW0")
PORT_DIPNAME( 0x0f, 0x00, DEF_STR( Coin_A ) )
PORT_DIPSETTING( 0x03, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x07, DEF_STR( 4C_2C ) )
PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x06, DEF_STR( 3C_2C ) )
PORT_DIPSETTING( 0x05, DEF_STR( 2C_2C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x0b, DEF_STR( 4C_5C ) )
PORT_DIPSETTING( 0x0f, "4 Coin/6 Credits" )
PORT_DIPSETTING( 0x0a, "3 Coin/5 Credits" )
PORT_DIPSETTING( 0x04, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x0e, "3 Coin/6 Credits" )
PORT_DIPSETTING( 0x09, DEF_STR( 2C_5C ) )
PORT_DIPSETTING( 0x0d, DEF_STR( 2C_6C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 1C_5C ) )
PORT_DIPSETTING( 0x0c, DEF_STR( 1C_6C ) )
PORT_DIPNAME( 0xf0, 0x00, DEF_STR( Coin_B ) )
PORT_DIPSETTING( 0x30, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x20, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x70, DEF_STR( 4C_2C ) )
PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x60, DEF_STR( 3C_2C ) )
PORT_DIPSETTING( 0x50, DEF_STR( 2C_2C ) )
PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0xb0, DEF_STR( 4C_5C ) )
PORT_DIPSETTING( 0xf0, "4 Coin/6 Credits" )
PORT_DIPSETTING( 0xa0, "3 Coin/5 Credits" )
PORT_DIPSETTING( 0x40, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0xe0, "3 Coin/6 Credits" )
PORT_DIPSETTING( 0x90, DEF_STR( 2C_5C ) )
PORT_DIPSETTING( 0xd0, DEF_STR( 2C_6C ) )
PORT_DIPSETTING( 0x80, DEF_STR( 1C_5C ) )
PORT_DIPSETTING( 0xc0, DEF_STR( 1C_6C ) )
PORT_MODIFY("DSW1")
PORT_DIPNAME( 0x03, 0x01, DEF_STR( Lives ) )
PORT_DIPSETTING( 0x00, "2" )
PORT_DIPSETTING( 0x01, "3" )
PORT_DIPSETTING( 0x02, "4" )
PORT_DIPSETTING( 0x03, "5" )
PORT_DIPUNUSED( 0x04, IP_ACTIVE_HIGH )
PORT_DIPNAME( 0x18, 0x08, DEF_STR( Bonus_Life ) )
PORT_DIPSETTING( 0x10, "30k, 50k and 100k" )
PORT_DIPSETTING( 0x08, "50k and 100k" )
PORT_DIPSETTING( 0x18, "100k and 200k" )
PORT_DIPSETTING( 0x00, DEF_STR( None ) )
PORT_DIPUNUSED( 0x20, IP_ACTIVE_HIGH )
PORT_DIPNAME( 0xc0, 0x80, DEF_STR( Difficulty ) )
PORT_DIPSETTING( 0xc0, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x80, DEF_STR( Normal ) )
PORT_DIPSETTING( 0x40, DEF_STR( Hard ) )
PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
INPUT_PORTS_END
/*************************************
*
* Graphics layouts
*
*************************************/
static const gfx_layout char_layout =
{
8,8,
RGN_FRAC(1,1),
4,
{ STEP4(0,2) },
{ 1, 0, 8*8+1, 8*8+0, 16*8+1, 16*8+0, 24*8+1, 24*8+0 },
{ STEP8(0,8) },
32*8
};
static const gfx_layout tile_layout =
{
16,16,
RGN_FRAC(1,2),
4,
{ RGN_FRAC(1,2)+0, RGN_FRAC(1,2)+4, 0, 4 },
{ 3, 2, 1, 0, 16*8+3, 16*8+2, 16*8+1, 16*8+0,
32*8+3, 32*8+2, 32*8+1, 32*8+0, 48*8+3, 48*8+2, 48*8+1, 48*8+0 },
{ STEP16(0,8) },
64*8
};
static GFXDECODE_START( gfx_ddragon )
GFXDECODE_ENTRY( "gfx1", 0, char_layout, 0, 8 ) /* colors 0-127 */
GFXDECODE_ENTRY( "gfx2", 0, tile_layout, 128, 8 ) /* colors 128-255 */
GFXDECODE_ENTRY( "gfx3", 0, tile_layout, 256, 8 ) /* colors 256-383 */
GFXDECODE_END
/*************************************
*
* Machine drivers
*
*************************************/
void ddragon_state::ddragon(machine_config &config)
{
/* basic machine hardware */
HD6309E(config, m_maincpu, MAIN_CLOCK / 4); /* HD63C09EP, 3 MHz */
m_maincpu->set_addrmap(AS_PROGRAM, &ddragon_state::ddragon_map);
TIMER(config, "scantimer").configure_scanline(FUNC(ddragon_state::ddragon_scanline), "screen", 0, 1);
hd63701y0_cpu_device &subcpu(HD63701Y0(config, m_subcpu, MAIN_CLOCK / 2)); /* HD63701Y0P, 6 MHz / 4 internally */
subcpu.set_addrmap(AS_PROGRAM, &ddragon_state::sub_map);
subcpu.out_p6_cb().set(FUNC(ddragon_state::sub_port6_w));
MC6809(config, m_soundcpu, MAIN_CLOCK / 2); /* HD68A09P, 6 MHz / 4 internally */
m_soundcpu->set_addrmap(AS_PROGRAM, &ddragon_state::sound_map);
config.set_maximum_quantum(attotime::from_hz(60000)); /* heavy interleaving to sync up sprite<->main CPUs */
/* video hardware */
GFXDECODE(config, m_gfxdecode, m_palette, gfx_ddragon);
PALETTE(config, m_palette).set_format(palette_device::xBGR_444, 512);
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_raw(PIXEL_CLOCK, 384, 0, 256, 272, 0, 240);
m_screen->set_screen_update(FUNC(ddragon_state::screen_update_ddragon));
m_screen->set_palette(m_palette);
/* sound hardware */
SPEAKER(config, "mono").front_center();
GENERIC_LATCH_8(config, m_soundlatch);
m_soundlatch->data_pending_callback().set_inputline(m_soundcpu, M6809_IRQ_LINE);
ym2151_device &fmsnd(YM2151(config, "fmsnd", SOUND_CLOCK));
fmsnd.irq_handler().set_inputline(m_soundcpu, M6809_FIRQ_LINE);
fmsnd.add_route(0, "mono", 0.60);
fmsnd.add_route(1, "mono", 0.60);
MSM5205(config, m_adpcm[0], MAIN_CLOCK / 32);
m_adpcm[0]->vck_legacy_callback().set(FUNC(ddragon_state::dd_adpcm_int_1)); /* interrupt function */
m_adpcm[0]->set_prescaler_selector(msm5205_device::S48_4B); /* 8kHz */
m_adpcm[0]->add_route(ALL_OUTPUTS, "mono", 0.50);
MSM5205(config, m_adpcm[1], MAIN_CLOCK / 32);
m_adpcm[1]->vck_legacy_callback().set(FUNC(ddragon_state::dd_adpcm_int_2)); /* interrupt function */
m_adpcm[1]->set_prescaler_selector(msm5205_device::S48_4B); /* 8kHz */
m_adpcm[1]->add_route(ALL_OUTPUTS, "mono", 0.50);
}
void ddragon_state::ddragonb(machine_config &config)