/
bullet.cpp
1307 lines (1014 loc) · 34.1 KB
/
bullet.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// license:BSD-3-Clause
// copyright-holders:Curt Coder
/*
Wave Mate Bullet
PCB Layout
----------
|-------------------------------------------|
| CN7 CN6 |
| PIO |
| FDC |
| 4164 4164 CN5 |
| 4164 4164 SW1 CN2|
| 4164 4164 |
| 4164 4164 PROM |
| 4164 4164 4.9152MHz |
| 4164 4164 16MHz DMA CPU |
| 4164 4164 |
| 4164 4164 CN4 CN3 CN1|
| |
| DART CTC |
| CN8 |
|-------------------------------------------|
Notes:
Relevant IC's shown.
CPU - SGS Z80ACPUB1 Z80A CPU
DMA - Zilog Z8410APS Z80A DMA
PIO - SGS Z80APIOB1 Z80A PIO
DART - Zilog Z8470APS Z80A DART
CTC - Zilog Z8430APS Z80A CTC
FDC - Synertek SY1793-02 FDC
PROM - AMD AM27S190C 32x8 TTL PROM
4164 - Fujitsu MB8264-15 64Kx1 RAM
CN1 - 2x25 PCB header, external DMA bus
CN2 - 2x17 PCB header, Winchester / 2x25 header, SCSI (in board revision E)
CN3 - 2x5 PCB header, RS-232 A (system console)
CN4 - 2x5 PCB header, RS-232 B
CN5 - 2x17 PCB header, Centronics
CN6 - 2x25 PCB header, 8" floppy drives
CN7 - 2x17 PCB header, 5.25" floppy drives
CN8 - 4-pin Molex
*/
/*
TODO:
- memory banking is broken
- z80dart wait/ready
- IMI 7710 Winchester controller
chdman createhd -o imi7710.chd -chs 350,3,10 -ss 1024
- revision E model
*/
#include "emu.h"
#include "bullet.h"
#include "bus/rs232/rs232.h"
#include "bus/scsi/scsihd.h"
#include "softlist.h"
//**************************************************************************
// MACROS / CONSTANTS
//**************************************************************************
// DMA ready sources
enum
{
FDRDY = 0,
DARTARDY,
DARTBRDY,
WINRDY,
EXRDY1,
EXRDY2
};
#define SEG0 \
BIT(m_mbank, 0)
#define SEG5 \
BIT(m_mbank, 5)
#define DMB4 \
BIT(m_xdma0, 4)
#define DMB6 \
BIT(m_xdma0, 6)
//**************************************************************************
// READ/WRITE HANDLERS
//**************************************************************************
//-------------------------------------------------
// mreq_r -
//-------------------------------------------------
uint8_t bullet_state::mreq_r(offs_t offset)
{
uint8_t data = 0;
if (!m_brom && !BIT(offset, 5))
{
data = m_rom->base()[offset & 0x1f];
}
else
{
if (offset < 0xc000)
{
data = m_ram->pointer()[(m_segst << 16) | offset];
}
else
{
data = m_ram->pointer()[offset];
}
}
return data;
}
//-------------------------------------------------
// mreq_w -
//-------------------------------------------------
void bullet_state::mreq_w(offs_t offset, uint8_t data)
{
if (offset < 0xc000)
{
m_ram->pointer()[(m_segst << 16) | offset] = data;
}
else
{
m_ram->pointer()[offset] = data;
}
}
//-------------------------------------------------
// win_r -
//-------------------------------------------------
uint8_t bullet_state::win_r()
{
return 0;
}
//-------------------------------------------------
// wstrobe_w -
//-------------------------------------------------
void bullet_state::wstrobe_w(uint8_t data)
{
}
//-------------------------------------------------
// brom_r -
//-------------------------------------------------
uint8_t bullet_state::brom_r()
{
m_brom = 1;
return 0;
}
//-------------------------------------------------
// brom_w -
//-------------------------------------------------
void bullet_state::brom_w(uint8_t data)
{
m_brom = 1;
}
//-------------------------------------------------
// exdsk_w -
//-------------------------------------------------
void bullet_state::exdsk_w(uint8_t data)
{
/*
bit signal description
0 drive select 0
1 drive select 1
2 select 8" floppy
3 MSE select software control of port
4 SIDE select side 2
5 _MOTOR disable 5" floppy spindle motors
6
7 WPRC enable write precompensation
*/
if (BIT(data, 3))
{
m_exdsk_sw = true;
}
if (m_exdsk_sw)
{
// drive select
m_floppy = nullptr;
switch (data & 0x07)
{
// 5.25"
case 0: m_floppy = m_floppy0->get_device(); break;
case 1: m_floppy = m_floppy1->get_device(); break;
case 2: m_floppy = m_floppy2->get_device(); break;
case 3: m_floppy = m_floppy3->get_device(); break;
// 8"
case 4: m_floppy = m_floppy4->get_device(); break;
case 5: m_floppy = m_floppy5->get_device(); break;
case 6: m_floppy = m_floppy6->get_device(); break;
case 7: m_floppy = m_floppy7->get_device(); break;
}
m_fdc->set_floppy(m_floppy);
}
if (m_floppy)
{
// side select
m_floppy->ss_w(BIT(data, 4));
// floppy motor
m_floppy->mon_w(BIT(data, 5));
}
}
//-------------------------------------------------
// exdma_w -
//-------------------------------------------------
void bullet_state::exdma_w(uint8_t data)
{
/*
bit description
0 DMA ready source select 0
1 DMA ready source select 1
2 DMA ready source select 2
3 memory control 0
4 memory control 1
5
6
7
*/
m_exdma = data;
m_buf = BIT(data, 3);
update_dma_rdy();
}
//-------------------------------------------------
// hdcon_w -
//-------------------------------------------------
void bullet_state::hdcon_w(uint8_t data)
{
/*
bit signal description
0 PLO phase lock oscillator
1 RCD read clock frequency
2 EXC MB8877 clock frequency
3 DEN MB8877 density select
4 enable software control of mode
5
6
7
*/
if (BIT(data, 4))
{
m_hdcon_sw = true;
}
if (m_hdcon_sw)
{
// FDC clock
m_fdc->set_unscaled_clock(16_MHz_XTAL / (BIT(data, 2) ? 16 : 8));
// density select
m_fdc->dden_w(BIT(data, 3));
}
}
//-------------------------------------------------
// info_r -
//-------------------------------------------------
uint8_t bullet_state::info_r()
{
/*
bit signal description
0 SW1 DIP switch 1
1 SW2 DIP switch 2
2 SW3 DIP switch 3
3 SW4 DIP switch 4
4 HLDST floppy disk head load status
5 *XDCG floppy disk exchange (8" only)
6 FDIRQ FDC interrupt request line
7 FDDRQ FDC data request line
*/
uint8_t data = 0;
// DIP switches
data |= m_sw1->read() & 0x0f;
// floppy
data |= m_fdc->hld_r() << 4;
data |= (m_floppy ? m_floppy->dskchg_r() : 1) << 5;
data |= m_fdc->intrq_r() << 6;
data |= m_fdc->drq_r() << 7;
return data;
}
//-------------------------------------------------
// segst_w -
//-------------------------------------------------
void bullet_state::segst_w(uint8_t data)
{
m_segst = BIT(data, 0);
}
//-------------------------------------------------
// mreq_r -
//-------------------------------------------------
uint8_t bulletf_state::mreq_r(offs_t offset)
{
uint8_t data = 0;
if (!m_rome && !BIT(offset, 5))
{
data = m_rom->base()[offset & 0x1f];
}
else
{
if (offset < 0xc000)
{
if (!SEG5)
{
data = m_ram->pointer()[(SEG0 << 16) | offset];
}
else if (offset >= 0x8000)
{
data = m_ram->pointer()[0x1c000 + (offset - 0x8000)];
}
}
else
{
data = m_ram->pointer()[offset];
}
}
return data;
}
//-------------------------------------------------
// mreq_w -
//-------------------------------------------------
void bulletf_state::mreq_w(offs_t offset, uint8_t data)
{
if (offset < 0xc000)
{
if (!SEG5)
{
m_ram->pointer()[(SEG0 << 16) | offset] = data;
}
else if (offset >= 0x8000)
{
m_ram->pointer()[0x1c000 + (offset - 0x8000)] = data;
}
}
else
{
m_ram->pointer()[offset] = data;
}
}
//-------------------------------------------------
// xdma0_w -
//-------------------------------------------------
void bulletf_state::xdma0_w(uint8_t data)
{
/*
bit signal
0 device select (0=FDC, 1=SCSI)
1
2
3
4 DMB4 Source bank
5
6 DMB6 Destination bank
7
*/
m_rome = 1;
m_xdma0 = data;
}
//-------------------------------------------------
// xfdc_w -
//-------------------------------------------------
void bulletf_state::xfdc_w(uint8_t data)
{
/*
bit signal
0 Unit select number
1 Unit select number
2 Unit select number
3 Unit select number
4 Select side 2
5 Disable 3 & 5 inch spindle motors
6 Set for 1 MHz controller operation, reset for 2 MHz controller operation
7 Set to select single density
*/
// drive select
m_floppy = nullptr;
switch (data & 0x0f)
{
// 5.25"
case 0: m_floppy = m_floppy0->get_device(); break;
case 1: m_floppy = m_floppy1->get_device(); break;
case 2: m_floppy = m_floppy2->get_device(); break;
case 3: m_floppy = m_floppy3->get_device(); break;
// 8"
case 4: m_floppy = m_floppy4->get_device(); break;
case 5: m_floppy = m_floppy5->get_device(); break;
case 6: m_floppy = m_floppy6->get_device(); break;
case 7: m_floppy = m_floppy7->get_device(); break;
// 3.5"
case 8: m_floppy = m_floppy8->get_device(); break;
case 9: m_floppy = m_floppy9->get_device(); break;
}
m_fdc->set_floppy(m_floppy);
if (m_floppy)
{
// side select
m_floppy->ss_w(BIT(data, 4));
// floppy motor
m_floppy->mon_w(BIT(data, 5));
}
// FDC clock
m_fdc->set_unscaled_clock(16_MHz_XTAL / (BIT(data, 6) ? 16 : 8));
// density select
m_fdc->dden_w(BIT(data, 7));
}
//-------------------------------------------------
// mbank_w -
//-------------------------------------------------
void bulletf_state::mbank_w(uint8_t data)
{
/*
bit signal
0 Select active bank (0=bank 0, 1=bank 1)
1
2
3
4 Select system space overlay (0=no overlay, 1=overlay)
5
6
7
*/
m_mbank = data;
}
//-------------------------------------------------
// scsi_r -
//-------------------------------------------------
uint8_t bulletf_state::scsi_r()
{
uint8_t data = m_scsi_data_in->read();
m_scsibus->write_ack(1);
m_wack = 0;
update_dma_rdy();
return data;
}
//-------------------------------------------------
// scsi_w -
//-------------------------------------------------
void bulletf_state::scsi_w(uint8_t data)
{
m_scsi_data_out->write(data);
m_scsibus->write_ack(1);
m_wack = 0;
update_dma_rdy();
}
//-------------------------------------------------
// hwsts_r -
//-------------------------------------------------
uint8_t bulletf_state::hwsts_r()
{
/*
bit signal
0 CBUSY Centronics busy
1 SW2 DIP switch 2
2 SW3 DIP switch 3
3 FD2S *Floppy disk two sided
4 HLDST Floppy disk head load status
5 XDCG *Floppy disk exchange (8-inch only)
6 FDIRQ FDC interrupt request line
7 FDDRQ FDC data request line
*/
uint8_t data = 0;
// centronics busy
data |= m_centronics_busy;
// DIP switches
data |= m_sw1->read() & 0x06;
// floppy
data |= (m_floppy ? m_floppy->twosid_r() : 1) << 3;
data |= m_fdc->hld_r() << 4;
data |= (m_floppy ? m_floppy->dskchg_r() : 1) << 5;
data |= m_fdc->intrq_r() << 6;
data |= m_fdc->drq_r() << 7;
return data;
}
//**************************************************************************
// ADDRESS MAPS
//**************************************************************************
//-------------------------------------------------
// ADDRESS_MAP( bullet_mem )
//-------------------------------------------------
void bullet_state::bullet_mem(address_map &map)
{
map(0x0000, 0xffff).rw(FUNC(bullet_state::mreq_r), FUNC(bullet_state::mreq_w));
}
//-------------------------------------------------
// ADDRESS_MAP( bullet_io )
//-------------------------------------------------
void bullet_state::bullet_io(address_map &map)
{
map.global_mask(0x1f);
map(0x00, 0x03).rw(m_dart, FUNC(z80dart_device::ba_cd_r), FUNC(z80dart_device::ba_cd_w));
map(0x04, 0x07).rw(Z80PIO_TAG, FUNC(z80pio_device::read), FUNC(z80pio_device::write));
map(0x08, 0x0b).rw(m_ctc, FUNC(z80ctc_device::read), FUNC(z80ctc_device::write));
map(0x0c, 0x0c).mirror(0x03).rw(FUNC(bullet_state::win_r), FUNC(bullet_state::wstrobe_w));
map(0x10, 0x13).rw(m_fdc, FUNC(mb8877_device::read), FUNC(mb8877_device::write));
map(0x14, 0x14).rw(m_dmac, FUNC(z80dma_device::read), FUNC(z80dma_device::write));
map(0x15, 0x15).rw(FUNC(bullet_state::brom_r), FUNC(bullet_state::brom_w));
map(0x16, 0x16).w(FUNC(bullet_state::exdsk_w));
map(0x17, 0x17).w(FUNC(bullet_state::exdma_w));
map(0x18, 0x18).w(FUNC(bullet_state::hdcon_w));
map(0x19, 0x19).r(FUNC(bullet_state::info_r));
map(0x1a, 0x1a).w(FUNC(bullet_state::segst_w));
}
//-------------------------------------------------
// ADDRESS_MAP( bulletf_mem )
//-------------------------------------------------
void bulletf_state::bulletf_mem(address_map &map)
{
map(0x0000, 0xffff).rw(FUNC(bulletf_state::mreq_r), FUNC(bulletf_state::mreq_w));
}
//-------------------------------------------------
// ADDRESS_MAP( bulletf_io )
//-------------------------------------------------
void bulletf_state::bulletf_io(address_map &map)
{
map.global_mask(0x3f);
map(0x00, 0x03).rw(m_dart, FUNC(z80dart_device::ba_cd_r), FUNC(z80dart_device::ba_cd_w));
map(0x04, 0x07).rw(Z80PIO_TAG, FUNC(z80pio_device::read), FUNC(z80pio_device::write));
map(0x08, 0x0b).rw(m_ctc, FUNC(z80ctc_device::read), FUNC(z80ctc_device::write));
map(0x10, 0x13).rw(m_fdc, FUNC(mb8877_device::read), FUNC(mb8877_device::write));
map(0x14, 0x14).w(FUNC(bulletf_state::xdma0_w));
map(0x16, 0x16).w(FUNC(bulletf_state::xfdc_w));
map(0x17, 0x17).w(FUNC(bulletf_state::mbank_w));
map(0x19, 0x19).rw(FUNC(bulletf_state::scsi_r), FUNC(bulletf_state::scsi_w));
map(0x1a, 0x1a).rw(m_dmac, FUNC(z80dma_device::read), FUNC(z80dma_device::write));
map(0x1b, 0x1b).r(FUNC(bulletf_state::hwsts_r));
}
//**************************************************************************
// INPUT PORTS
//**************************************************************************
//-------------------------------------------------
// INPUT_PORTS( bullet )
//-------------------------------------------------
INPUT_PORTS_START( bullet )
PORT_START("SW1")
PORT_DIPUNUSED_DIPLOC( 0x01, IP_ACTIVE_LOW, "SW1:1" )
PORT_DIPUNUSED_DIPLOC( 0x02, IP_ACTIVE_LOW, "SW1:2" )
PORT_DIPUNUSED_DIPLOC( 0x04, IP_ACTIVE_LOW, "SW1:3" )
PORT_DIPUNUSED_DIPLOC( 0x08, IP_ACTIVE_LOW, "SW1:4" )
PORT_DIPNAME( 0xf0, 0x50, "Floppy Type" ) PORT_DIPLOCATION("SW1:5,6,7,8")
PORT_DIPSETTING( 0xf0, "5.25\" SD" )
PORT_DIPSETTING( 0x50, "5.25\" DD" )
PORT_DIPSETTING( 0x90, "8\" SD" )
PORT_DIPSETTING( 0x00, "8\" DD" )
INPUT_PORTS_END
//-------------------------------------------------
// INPUT_PORTS( bulletf )
//-------------------------------------------------
INPUT_PORTS_START( bulletf )
PORT_START("SW1")
PORT_DIPNAME( 0x01, 0x01, "SCSI Bus Termination" ) PORT_DIPLOCATION("SW1:1")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x01, DEF_STR( On ) )
PORT_DIPUNUSED_DIPLOC( 0x02, IP_ACTIVE_LOW, "SW1:2" )
PORT_DIPUNUSED_DIPLOC( 0x04, IP_ACTIVE_LOW, "SW1:3" )
PORT_DIPNAME( 0x08, 0x08, "Boot ROM Device" ) PORT_DIPLOCATION("SW1:4")
PORT_DIPSETTING( 0x00, "Onboard" )
PORT_DIPSETTING( 0x08, "EPROM" )
PORT_DIPNAME( 0xf0, 0xc0, "Floppy Type" ) PORT_DIPLOCATION("SW1:5,6,7,8")
PORT_DIPSETTING( 0x10, "3\" DD" )
PORT_DIPSETTING( 0xc0, "5.25\" SD" )
PORT_DIPSETTING( 0x40, "5.25\" DD" )
PORT_DIPSETTING( 0xa0, "8\" SD" )
PORT_DIPSETTING( 0x20, "8\" DD" )
INPUT_PORTS_END
//**************************************************************************
// DEVICE CONFIGURATION
//**************************************************************************
//-------------------------------------------------
// Z80CTC
//-------------------------------------------------
TIMER_DEVICE_CALLBACK_MEMBER(bullet_state::ctc_tick)
{
m_ctc->trg0(1);
m_ctc->trg0(0);
m_ctc->trg1(1);
m_ctc->trg1(0);
m_ctc->trg2(1);
m_ctc->trg2(0);
}
void bullet_state::dart_rxtxca_w(int state)
{
m_dart->txca_w(state);
m_dart->rxca_w(state);
}
//-------------------------------------------------
// Z80DART
//-------------------------------------------------
void bullet_state::dartardy_w(int state)
{
m_dartardy = state;
update_dma_rdy();
}
void bullet_state::dartbrdy_w(int state)
{
m_dartbrdy = state;
update_dma_rdy();
}
//-------------------------------------------------
// Z80DMA
//-------------------------------------------------
void bullet_state::update_dma_rdy()
{
int rdy = 1;
switch (m_exdma & 0x07)
{
case FDRDY:
rdy = m_fdrdy;
break;
case DARTARDY:
rdy = m_dartardy;
break;
case DARTBRDY:
rdy = m_dartbrdy;
break;
case WINRDY:
rdy = m_winrdy;
break;
case EXRDY1:
rdy = m_exrdy1;
break;
case EXRDY2:
rdy = m_exrdy2;
break;
}
m_dmac->rdy_w(rdy);
}
uint8_t bullet_state::dma_mreq_r(offs_t offset)
{
uint8_t data = m_ram->pointer()[(m_buf << 16) | offset];
if (BIT(m_exdma, 4))
{
m_buf = !m_buf;
}
return data;
}
void bullet_state::dma_mreq_w(offs_t offset, uint8_t data)
{
m_ram->pointer()[(m_buf << 16) | offset] = data;
if (BIT(m_exdma, 4))
{
m_buf = !m_buf;
}
}
uint8_t bullet_state::io_read_byte(offs_t offset)
{
return m_maincpu->space(AS_IO).read_byte(offset);
}
void bullet_state::io_write_byte(offs_t offset, uint8_t data)
{
m_maincpu->space(AS_IO).write_byte(offset, data);
}
//-------------------------------------------------
// Z80DMA for bulletf (not used currently)
//-------------------------------------------------
void bulletf_state::update_dma_rdy()
{
int rdy = 1;
if (BIT(m_xdma0, 0))
{
rdy = m_wack || m_wrdy;
}
else
{
rdy = m_fdrdy;
}
m_dmac->rdy_w(rdy);
}
uint8_t bulletf_state::dma_mreq_r(offs_t offset)
{
return m_ram->pointer()[(DMB4 << 16) | offset];
}
void bulletf_state::dma_mreq_w(offs_t offset, uint8_t data)
{
m_ram->pointer()[(DMB6 << 16) | offset] = data;
}
//-------------------------------------------------
// Z80PIO
//-------------------------------------------------
void bullet_state::write_centronics_busy(int state)
{
m_centronics_busy = state;
}
void bullet_state::write_centronics_perror(int state)
{
m_centronics_perror = state;
}
void bullet_state::write_centronics_select(int state)
{
m_centronics_select = state;
}
void bullet_state::write_centronics_fault(int state)
{
m_centronics_fault = state;
}
uint8_t bullet_state::pio_pb_r()
{
/*
bit signal description
0 centronics busy
1 centronics paper end
2 centronics selected
3 *FAULT centronics fault
4 external vector
5 WBUSDIR winchester bus direction
6 WCOMPLETE winchester command complete
7 *WINRDY winchester ready
*/
uint8_t data = 0;
// centronics
data |= m_centronics_busy;
data |= m_centronics_perror << 1;
data |= m_centronics_select << 2;
data |= m_centronics_fault << 3;
return data;
}
void bulletf_state::pio_pa_w(uint8_t data)
{
/*
bit signal
0 ATN
1 RST
2 SEL
3 BUSY
4 MSG
5 C/D
6 REQ
7 I/O
*/
m_scsibus->write_atn(BIT(data, 0));
m_scsibus->write_rst(BIT(data, 1));
m_scsibus->write_sel(BIT(data, 2));
}
void bulletf_state::cstrb_w(int state)
{
m_centronics->write_strobe(!state);
}
static void bullet_525_floppies(device_slot_interface &device)
{
device.option_add("525sd", FLOPPY_525_SD);
device.option_add("525dd", FLOPPY_525_DD);
device.option_add("525qd", FLOPPY_525_QD);
}
static void bullet_8_floppies(device_slot_interface &device)
{
device.option_add("8dssd", FLOPPY_8_DSSD);
device.option_add("8dsdd", FLOPPY_8_DSDD);
}
static void bullet_35_floppies(device_slot_interface &device)
{
device.option_add("35dd", FLOPPY_35_DD);
}
void bullet_state::fdc_drq_w(int state)
{
m_fdrdy = !state;
update_dma_rdy();
}
void bulletf_state::req_w(int state)
{
if (!state)
{
m_scsibus->write_ack(0);
m_wack = 1;
}
m_wrdy = !state;
update_dma_rdy();
m_scsi_ctrl_in->write_bit6(state);
}
static DEVICE_INPUT_DEFAULTS_START( terminal )
DEVICE_INPUT_DEFAULTS( "RS232_TXBAUD", 0xff, RS232_BAUD_9600 )
DEVICE_INPUT_DEFAULTS( "RS232_RXBAUD", 0xff, RS232_BAUD_9600 )
DEVICE_INPUT_DEFAULTS( "RS232_DATABITS", 0xff, RS232_DATABITS_8 )
DEVICE_INPUT_DEFAULTS( "RS232_PARITY", 0xff, RS232_PARITY_NONE )
DEVICE_INPUT_DEFAULTS( "RS232_STOPBITS", 0xff, RS232_STOPBITS_1 )
DEVICE_INPUT_DEFAULTS_END
//-------------------------------------------------
// z80_daisy_config daisy_chain
//-------------------------------------------------
static const z80_daisy_config daisy_chain[] =
{
{ Z80DMA_TAG },
{ Z80DART_TAG },
{ Z80PIO_TAG },
{ Z80CTC_TAG },
{ nullptr }
};