/
apple2gs.cpp
4037 lines (3441 loc) · 110 KB
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apple2gs.cpp
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// license:BSD-3-Clause
// copyright-holders:R. Belmont
/***************************************************************************
apple2gs.cpp - Apple IIgs
Next generation driver written June 2018 by R. Belmont.
Thanks to the original Apple IIgs driver's authors: Nathan Woods and R. Belmont
Thanks also to the Apple II Documentation Project/Antoine Vignau, Peter Ferrie, and Olivier Galibert.
Unique hardware configurations:
- ROM 00/01: original motherboard, 256K of RAM (banks 00/01/E0/E1 only), FPI chip manages fast/slow side
- ROM 03: revised motherboard, 1M of RAM (banks 00/01/->0F/E0/E1), CYA chip replaces FPI
- Expanded IIe: ROM 00/01 motherboard in a IIe case with a IIe keyboard rather than ADB
- "Mark Twain" prototype: ROM 3 hardware, SWIM1 instead of IWM, built-in floppy, integrated High-Speed SCSI Card
and internal SCSI HDD, 2 SIMM slots for RAM expansion instead of the proprietary memory slot of the previous IIgs.
Only 5 slots: slots 5 and 7 are missing (5 for the SuperDrive, 7 for the SCSI).
Timing in terms of the 14M 14.3181818 MHz clock (1/2 of the 28.6363636 master clock):
- 1 2.8 MHz 65816 cycle is 5 14M clocks.
- The Mega II 1 MHz side runs for 64 cycles at 14 14M clocks and every 65th is stretched to 16 14M clocks.
This allows 8-bit Apple II raster demos to work. Each scanline is (64*14) + 16 = 912 14M clocks.
Due to this stretch, which does not occur on the fast side, the fast and 1 Mhz sides drift from each other
and sync up every 22800 14M clocks (25 scan lines).
- Accesses to the 1 MHz side incur a side-sync penalty (waiting for the start of the next 1 MHz cycle).
- Every 50 14M clocks (10 65816 cycles) DRAM refresh occurs for 5 14M clocks
* During this time, CPU accesses to ROM, Mega II side I/O, or banks E0/E1 are not penalized (but a side-sync penalty is incurred for the 1 MHz side)
* Accesses to banks 00-7F are penalized except for I/O in banks 0/1.
- ROM accesses always run at full speed.
One video line is: 6 cycles of right border, 13 cycles of hblank, 6 cycles of left border, and 40 cycles of active video
((6*14)*2) + 560 = 728 (total for A2 modes) htotal = 910 (65 * 14)
((6*16)*2) + 640 = 832 (total for SHR) htotal = 1040 (65 * 16)
FF6ACF is speed test in ROM
Diags:
A138 = scanline interrupt test (raster is too long to pass this)
A179 = pass
A17C = fail 1
A0F1 = fail 2
ZipGS notes:
$C059 is the GS settings register
bit 3: CPS Follow
bit 4: Counter Delay
bit 5: AppleTalk Delay
bit 6: Joystick Delay (reverse logic: 0 = delay is ON)
bit 7: C/D cache disable
$C05D is the speed percentage:
$F0 = 6%, $E0 = 12%, $D0 = 18%, $C0 = 25%, $B0 = 31%, $A0 = 37%, $90 = 43%, $80 = 50%,
$70 = 56%, $60 = 62%, $50 = 68%, $40 = 75%, $30 = 81%, $20 = 87%, $10 = 93%, $00 = 100%
***************************************************************************/
#include "emu.h"
#include "apple2video.h"
#include "apple2common.h"
// #include "machine/apple2host.h"
#include "macadb.h"
#include "macrtc.h"
#include "bus/a2bus/a2bus.h"
#include "bus/a2bus/cards.h"
#include "bus/a2gameio/gameio.h"
#include "bus/rs232/rs232.h"
#include "cpu/g65816/g65816.h"
#include "cpu/m6502/m5074x.h"
#include "machine/bankdev.h"
#include "machine/ram.h"
#include "machine/timer.h"
#include "machine/z80scc.h"
#include "sound/es5503.h"
#include "sound/spkrdev.h"
#include "machine/applefdintf.h"
#include "machine/iwm.h"
#include "machine/swim1.h"
#include "screen.h"
#include "softlist_dev.h"
#include "speaker.h"
#include "utf8.h"
namespace {
// various timing standards
#define A2GS_MASTER_CLOCK (XTAL(28'636'363))
#define A2GS_14M (A2GS_MASTER_CLOCK/2)
#define A2GS_7M (A2GS_MASTER_CLOCK/4)
#define A2GS_1M (A2GS_MASTER_CLOCK/28)
#define A2GS_UPPERBANK_TAG "inhbank"
#define A2GS_AUXUPPER_TAG "inhaux"
#define A2GS_00UPPER_TAG "inh00"
#define A2GS_01UPPER_TAG "inh01"
#define A2GS_C300_TAG "c3bank"
#define A2GS_LCBANK_TAG "lcbank"
#define A2GS_LCAUX_TAG "lcaux"
#define A2GS_LC00_TAG "lc00"
#define A2GS_LC01_TAG "lc01"
#define A2GS_B0CXXX_TAG "bnk0atc"
#define A2GS_B1CXXX_TAG "bnk1atc"
#define A2GS_B00000_TAG "b0r00bank"
#define A2GS_B00200_TAG "b0r02bank"
#define A2GS_B00400_TAG "b0r04bank"
#define A2GS_B00800_TAG "b0r08bank"
#define A2GS_B02000_TAG "b0r20bank"
#define A2GS_B04000_TAG "b0r40bank"
#define A2GS_KBD_SPEC_TAG "keyb_special"
class apple2gs_state : public driver_device
{
public:
apple2gs_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_screen(*this, "screen"),
m_scantimer(*this, "scantimer"),
m_acceltimer(*this, "acceltimer"),
m_adbmicro(*this, "adbmicro"),
m_macadb(*this, "macadb"),
m_ram(*this, "ram"),
m_rom(*this, "maincpu"),
m_docram(*this, "docram"),
m_video(*this, "a2video"),
m_rtc(*this, "rtc"),
m_a2bus(*this, "a2bus"),
m_a2common(*this, "a2common"),
// m_a2host(*this, "a2host"),
m_gameio(*this, "gameio"),
m_speaker(*this, "speaker"),
m_upperbank(*this, A2GS_UPPERBANK_TAG),
m_upperaux(*this, A2GS_AUXUPPER_TAG),
m_upper00(*this, A2GS_00UPPER_TAG),
m_upper01(*this, A2GS_01UPPER_TAG),
m_c300bank(*this, A2GS_C300_TAG),
m_b0_0000bank(*this, A2GS_B00000_TAG),
m_b0_0200bank(*this, A2GS_B00200_TAG),
m_b0_0400bank(*this, A2GS_B00400_TAG),
m_b0_0800bank(*this, A2GS_B00800_TAG),
m_b0_2000bank(*this, A2GS_B02000_TAG),
m_b0_4000bank(*this, A2GS_B04000_TAG),
m_e0_0000bank(*this, "e0_0000_bank"),
m_e0_0200bank(*this, "e0_0200_bank"),
m_e0_0400bank(*this, "e0_0400_bank"),
m_e0_0800bank(*this, "e0_0800_bank"),
m_e0_2000bank(*this, "e0_2000_bank"),
m_e0_4000bank(*this, "e0_4000_bank"),
m_lcbank(*this, A2GS_LCBANK_TAG),
m_lcaux(*this, A2GS_LCAUX_TAG),
m_lc00(*this, A2GS_LC00_TAG),
m_lc01(*this, A2GS_LC01_TAG),
m_bank0_atc(*this, A2GS_B0CXXX_TAG),
m_bank1_atc(*this, A2GS_B1CXXX_TAG),
m_scc(*this, "scc"),
m_doc(*this, "doc"),
m_iwm(*this, "fdc"),
m_floppy(*this, "fdc:%d", 0U),
m_sysconfig(*this, "a2_config")
{
m_cur_floppy = nullptr;
m_devsel = 0;
m_diskreg = 0;
}
void apple2gs(machine_config &config);
void apple2gsr1(machine_config &config);
void apple2gsmt(machine_config &config);
void rom1_init() { m_is_rom3 = false; }
void rom3_init() { m_is_rom3 = true; }
protected:
virtual void machine_start() override;
virtual void machine_reset() override;
private:
required_device<g65816_device> m_maincpu;
required_device<screen_device> m_screen;
required_device<timer_device> m_scantimer, m_acceltimer;
required_device<m5074x_device> m_adbmicro;
required_device<macadb_device> m_macadb;
required_device<ram_device> m_ram;
required_region_ptr<u8> m_rom;
required_shared_ptr<u8> m_docram;
required_device<a2_video_device> m_video;
required_device<rtc3430042_device> m_rtc;
required_device<a2bus_device> m_a2bus;
required_device<apple2_common_device> m_a2common;
// required_device<apple2_host_device> m_a2host;
required_device<apple2_gameio_device> m_gameio;
required_device<speaker_sound_device> m_speaker;
memory_view m_upperbank, m_upperaux, m_upper00, m_upper01;
required_device<address_map_bank_device> m_c300bank;
memory_view m_b0_0000bank, m_b0_0200bank, m_b0_0400bank, m_b0_0800bank, m_b0_2000bank, m_b0_4000bank;
memory_view m_e0_0000bank, m_e0_0200bank, m_e0_0400bank, m_e0_0800bank, m_e0_2000bank, m_e0_4000bank;
memory_view m_lcbank, m_lcaux, m_lc00, m_lc01, m_bank0_atc, m_bank1_atc;
required_device<z80scc_device> m_scc;
required_device<es5503_device> m_doc;
required_device<applefdintf_device> m_iwm;
required_device_array<floppy_connector, 4> m_floppy;
required_ioport m_sysconfig;
static constexpr int CNXX_UNCLAIMED = -1;
static constexpr int CNXX_INTROM = -2;
enum glu_reg_names
{
// these are the MCU-visible registers
GLU_KEY_DATA = 0, // MCU W
GLU_COMMAND, // MCU R
GLU_MOUSEX, // MCU W
GLU_MOUSEY, // MCU W
GLU_KG_STATUS, // MCU R
GLU_ANY_KEY_DOWN, // MCU W
GLU_KEYMOD, // MCU W
GLU_DATA, // MCU W
GLU_C000, // 816 R
GLU_C010, // 816 RW
GLU_SYSSTAT // 816 R/(limited) W
};
static constexpr u8 KGS_ANY_KEY_DOWN = 0x01;
static constexpr u8 KGS_KEYSTROBE = 0x10;
static constexpr u8 KGS_DATA_FULL = 0x20;
static constexpr u8 KGS_COMMAND_FULL = 0x40;
static constexpr u8 KGS_MOUSEX_FULL = 0x80;
static constexpr u8 GLU_STATUS_CMDFULL = 0x01;
static constexpr u8 GLU_STATUS_MOUSEXY = 0x02;
static constexpr u8 GLU_STATUS_KEYDATIRQEN = 0x04;
static constexpr u8 GLU_STATUS_KEYDATIRQ = 0x08;
static constexpr u8 GLU_STATUS_DATAIRQEN = 0x10;
static constexpr u8 GLU_STATUS_DATAIRQ = 0x20;
static constexpr u8 GLU_STATUS_MOUSEIRQEN = 0x40;
static constexpr u8 GLU_STATUS_MOUSEIRQ = 0x080;
static constexpr u8 SHAD_IOLC = 0x40; // I/O and language card inhibit for banks 00/01
static constexpr u8 SHAD_TXTPG2 = 0x20; // inhibits text-page 2 shadowing in both banks (ROM 03 h/w only)
static constexpr u8 SHAD_AUXHIRES = 0x10; // inhibits bank 01 hi-res region shadowing
static constexpr u8 SHAD_SUPERHIRES = 0x08; // inhibits bank 01 super-hi-res region shadowing
static constexpr u8 SHAD_HIRESPG2 = 0x04; // inhibits hi-res page 2 shadowing in both banks
static constexpr u8 SHAD_HIRESPG1 = 0x02; // inhibits hi-res page 1 shadowing in both banks
static constexpr u8 SHAD_TXTPG1 = 0x01; // inhibits text-page 1 shadowing in both banks
static constexpr u8 SPEED_HIGH = 0x80; // full 2.8 MHz speed when set, Apple II 1 MHz when clear
[[maybe_unused]] static constexpr u8 SPEED_POWERON = 0x40; // ROM 03 only; indicates machine turned on by power switch (as opposed to ?)
static constexpr u8 SPEED_ALLBANKS = 0x10; // enables bank 0/1 shadowing in all banks (not supported)
[[maybe_unused]] static constexpr u8 SPEED_DISKIISL7 = 0x08; // enable Disk II motor on detect for slot 7
[[maybe_unused]] static constexpr u8 SPEED_DISKIISL6 = 0x04; // enable Disk II motor on detect for slot 6
[[maybe_unused]] static constexpr u8 SPEED_DISKIISL5 = 0x02; // enable Disk II motor on detect for slot 5
[[maybe_unused]] static constexpr u8 SPEED_DISKIISL4 = 0x01; // enable Disk II motor on detect for slot 4
static constexpr u8 DISKREG_HDSEL = 7; // select signal for 3.5" Sony drives
static constexpr u8 DISKREG_35SEL = 6; // 1 to enable 3.5" drives, 0 to chain through to 5.25"
enum irq_sources
{
IRQS_DOC = 0,
IRQS_SCAN = 1,
IRQS_ADB = 2,
IRQS_VBL = 3,
IRQS_SECOND = 4,
IRQS_QTRSEC = 5,
IRQS_SLOT = 6,
IRQS_SCC = 7
};
static constexpr u8 INTFLAG_IRQASSERTED = 0x01;
[[maybe_unused]] static constexpr u8 INTFLAG_M2MOUSEMOVE = 0x02;
[[maybe_unused]] static constexpr u8 INTFLAG_M2MOUSESW = 0x04;
static constexpr u8 INTFLAG_VBL = 0x08;
static constexpr u8 INTFLAG_QUARTER = 0x10;
static constexpr u8 INTFLAG_AN3 = 0x20;
[[maybe_unused]] static constexpr u8 INTFLAG_MOUSEDOWNLAST = 0x40;
[[maybe_unused]] static constexpr u8 INTFLAG_MOUSEDOWN = 0x80;
[[maybe_unused]] static constexpr u8 VGCINT_EXTERNALEN = 0x01;
static constexpr u8 VGCINT_SCANLINEEN = 0x02;
static constexpr u8 VGCINT_SECONDENABLE = 0x04;
[[maybe_unused]] static constexpr u8 VGCINT_EXTERNAL = 0x10;
static constexpr u8 VGCINT_SCANLINE = 0x20;
static constexpr u8 VGCINT_SECOND = 0x40;
static constexpr u8 VGCINT_ANYVGCINT = 0x80;
enum adbstate_t
{
ADBSTATE_IDLE,
ADBSTATE_INCOMMAND,
ADBSTATE_INRESPONSE
};
bool m_adb_line = false;
address_space *m_maincpu_space = nullptr;
TIMER_DEVICE_CALLBACK_MEMBER(apple2_interrupt);
TIMER_DEVICE_CALLBACK_MEMBER(accel_timer);
void palette_init(palette_device &palette);
u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
void apple2gs_map(address_map &map);
void vectors_map(address_map &map);
void a2gs_es5503_map(address_map &map);
void c300bank_map(address_map &map);
void phases_w(uint8_t phases);
void sel35_w(int sel35);
void devsel_w(uint8_t devsel);
void hdsel_w(int hdsel);
floppy_image_device *m_cur_floppy = nullptr;
int m_devsel = 0;
u8 m_diskreg = 0;
u8 auxram0000_r(offs_t offset);
void auxram0000_w(offs_t offset, u8 data);
u8 b0ram0000_r(offs_t offset);
void b0ram0000_w(offs_t offset, u8 data);
u8 b0ram0200_r(offs_t offset);
void b0ram0200_w(offs_t offset, u8 data);
u8 b0ram0400_r(offs_t offset);
void b0ram0400_w(offs_t offset, u8 data);
u8 b0ram0800_r(offs_t offset);
void b0ram0800_w(offs_t offset, u8 data);
u8 b0ram2000_r(offs_t offset);
void b0ram2000_w(offs_t offset, u8 data);
u8 b0ram4000_r(offs_t offset);
void b0ram4000_w(offs_t offset, u8 data);
u8 b1ram0000_r(offs_t offset);
void b1ram0000_w(offs_t offset, u8 data);
u8 b1ram0200_r(offs_t offset);
void b1ram0200_w(offs_t offset, u8 data);
u8 b1ram0400_r(offs_t offset);
void b1ram0400_w(offs_t offset, u8 data);
u8 b1ram0800_r(offs_t offset);
void b1ram0800_w(offs_t offset, u8 data);
u8 b1ram2000_r(offs_t offset);
void b1ram2000_w(offs_t offset, u8 data);
u8 b1ram4000_r(offs_t offset);
void b1ram4000_w(offs_t offset, u8 data);
template <int Addr> u8 e0ram_r(offs_t offset);
template <int Addr> void e0ram_w(offs_t offset, u8 data);
template <int Addr> u8 e1ram_r(offs_t offset);
template <int Addr> void e1ram_w(offs_t offset, u8 data);
u8 c000_r(offs_t offset);
void c000_w(offs_t offset, u8 data);
u8 c080_r(offs_t offset);
void c080_w(offs_t offset, u8 data);
u8 c100_r(offs_t offset);
void c100_w(offs_t offset, u8 data);
u8 c300_r(offs_t offset);
u8 c300_int_r(offs_t offset);
void c300_w(offs_t offset, u8 data);
u8 c400_r(offs_t offset);
void c400_w(offs_t offset, u8 data);
u8 c800_r(offs_t offset);
void c800_w(offs_t offset, u8 data);
u8 inh_r(offs_t offset);
void inh_w(offs_t offset, u8 data);
u8 lc_r(offs_t offset);
void lc_w(offs_t offset, u8 data);
u8 lc_aux_r(offs_t offset);
void lc_aux_w(offs_t offset, u8 data);
u8 lc_00_r(offs_t offset);
void lc_00_w(offs_t offset, u8 data);
u8 lc_01_r(offs_t offset);
void lc_01_w(offs_t offset, u8 data);
u8 bank0_c000_r(offs_t offset);
void bank0_c000_w(offs_t offset, u8 data);
u8 bank1_0000_r(offs_t offset);
void bank1_0000_sh_w(offs_t offset, u8 data);
u8 bank1_c000_r(offs_t offset);
void bank1_c000_w(offs_t offset, u8 data);
void a2bus_irq_w(int state);
void a2bus_nmi_w(int state);
void a2bus_inh_w(int state);
void doc_irq_w(int state);
void scc_irq_w(int state);
u8 doc_adc_read();
u8 apple2gs_read_vector(offs_t offset);
u8 keyglu_mcu_read(u8 offset);
void keyglu_mcu_write(u8 offset, u8 data);
u8 keyglu_816_read(u8 offset);
void keyglu_816_write(u8 offset, u8 data);
u8 m_adb_p2_last, m_adb_p3_last;
int m_adb_reset_freeze = 0;
void keyglu_regen_irqs();
u8 adbmicro_p0_in();
u8 adbmicro_p1_in();
u8 adbmicro_p2_in();
u8 adbmicro_p3_in();
void adbmicro_p0_out(u8 data);
void adbmicro_p1_out(u8 data);
void adbmicro_p2_out(u8 data);
void adbmicro_p3_out(u8 data);
void set_adb_line(int linestate);
offs_t dasm_trampoline(std::ostream &stream, offs_t pc, const util::disasm_interface::data_buffer &opcodes, const util::disasm_interface::data_buffer ¶ms);
void wdm_trampoline(offs_t offset, u8 data) { }; //m_a2host->wdm_w(space, offset, data); }
bool m_is_rom3 = false;
int m_speaker_state = 0;
double m_joystick_x1_time = 0, m_joystick_y1_time = 0, m_joystick_x2_time = 0, m_joystick_y2_time = 0;
int m_inh_slot = 0, m_cnxx_slot = 0;
int m_motoroff_time = 0;
bool m_romswitch = false;
bool m_an0 = false, m_an1 = false, m_an2 = false, m_an3 = false;
bool m_vbl = false;
int m_irqmask = 0;
bool m_intcxrom = false;
bool m_slotc3rom = false;
bool m_altzp = false;
bool m_ramrd = false, m_ramwrt = false;
bool m_lcram = false, m_lcram2 = false, m_lcprewrite = false, m_lcwriteenable = false;
bool m_ioudis = false;
bool m_rombank = false;
u8 m_shadow = 0, m_speed = 0, m_textcol = 0;
u8 m_motors_active = 0, m_slotromsel = 0, m_intflag = 0, m_vgcint = 0, m_inten = 0;
bool m_last_speed = false;
// Sound GLU variables
u8 m_sndglu_ctrl = 0;
int m_sndglu_addr = 0;
int m_sndglu_dummy_read = 0;
// Key GLU variables
u8 m_glu_regs[12]{}, m_glu_bus = 0;
bool m_glu_mcu_read_kgs = false, m_glu_816_read_dstat = false, m_glu_mouse_read_stat = false;
int m_glu_kbd_y = 0;
u8 *m_ram_ptr = nullptr;
int m_ram_size = 0;
u8 m_megaii_ram[0x20000]{}; // 128K of "slow RAM" at $E0/0000
int m_inh_bank = 0;
bool m_slot_irq = false;
double m_x_calibration = 0, m_y_calibration = 0;
device_a2bus_card_interface *m_slotdevice[8]{};
u32 m_slow_counter = 0;
// clock/BRAM
u8 m_clkdata = 0, m_clock_control = 0;
u8 m_clock_frame = 0;
void do_io(int offset);
u8 read_floatingbus();
void update_slotrom_banks();
void lc_update(int offset, bool writing);
u8 read_slot_rom(int slotbias, int offset);
void write_slot_rom(int slotbias, int offset, u8 data);
u8 read_int_rom(int slotbias, int offset);
void auxbank_update();
void raise_irq(int irq);
void lower_irq(int irq);
void update_speed();
int get_vpos();
void process_clock();
// ZipGS stuff
bool m_accel_unlocked = false;
bool m_accel_fast = false;
bool m_accel_present = false;
bool m_accel_temp_slowdown = false;
int m_accel_stage = 0;
u32 m_accel_speed = 0;
u8 m_accel_slotspk = 0, m_accel_gsxsettings = 0, m_accel_percent = 0;
void accel_full_speed()
{
bool isfast = false;
if (m_speed & SPEED_HIGH)
{
isfast = true;
}
if ((m_motors_active & (m_speed & 0x0f)) != 0)
{
isfast = false;
}
if (isfast)
{
m_maincpu->set_unscaled_clock(m_accel_speed);
}
else
{
m_maincpu->set_unscaled_clock(1021800);
}
}
void accel_normal_speed()
{
bool isfast = false;
if (m_speed & SPEED_HIGH)
{
isfast = true;
}
if ((m_motors_active & (m_speed & 0x0f)) != 0)
{
isfast = false;
}
if (isfast)
{
m_maincpu->set_unscaled_clock(A2GS_14M/5);
}
else
{
m_maincpu->set_unscaled_clock(1021800);
}
}
void accel_slot(int slot);
};
// FF6ACF is speed test routine in ROM 3
// slow_cycle() - take a 1 MHz cycle. Theory: a 2.8 MHz cycle is 14M / 5.
// 1 MHz is 14M / 14. 14/5 = 2.8 * 65536 (16.16 fixed point) = 0x2cccd.
#define slow_cycle() \
{ \
if (!machine().side_effects_disabled() && m_last_speed) \
{\
m_slow_counter += 0x0002cccd; \
int cycles = (m_slow_counter >> 16) & 0xffff; \
m_slow_counter &= 0xffff; \
m_maincpu->adjust_icount(-cycles); \
} \
}
offs_t apple2gs_state::dasm_trampoline(std::ostream &stream, offs_t pc, const util::disasm_interface::data_buffer &opcodes, const util::disasm_interface::data_buffer ¶ms)
{
return m_a2common->dasm_override_GS(stream, pc, opcodes, params);
}
void apple2gs_state::a2bus_irq_w(int state)
{
if (state == ASSERT_LINE)
{
raise_irq(IRQS_SLOT);
m_slot_irq = true;
}
else
{
lower_irq(IRQS_SLOT);
}
}
void apple2gs_state::a2bus_nmi_w(int state)
{
m_maincpu->set_input_line(INPUT_LINE_NMI, state);
}
// TODO: this assumes /INH only on ROM, needs expansion to support e.g. phantom-slotting cards and etc.
void apple2gs_state::a2bus_inh_w(int state)
{
if (state == ASSERT_LINE)
{
// assume no cards are pulling /INH
m_inh_slot = -1;
// scan the slots to figure out which card(s) are INHibiting stuff
for (int i = 0; i <= 7; i++)
{
if (m_slotdevice[i])
{
// this driver only can inhibit from 0xd000-0xffff
if ((m_slotdevice[i]->inh_start() == 0xd000) &&
(m_slotdevice[i]->inh_end() == 0xffff))
{
if ((m_slotdevice[i]->inh_type() & INH_READ) == INH_READ)
{
if (m_inh_bank != 1)
{
m_upperbank.select(1);
m_upperaux.select(1);
m_upper00.select(1);
m_upper01.select(1);
m_inh_bank = 1;
}
}
else
{
if (m_inh_bank != 0)
{
m_upperbank.select(0);
m_upperaux.select(0);
m_upper00.select(0);
m_upper01.select(0);
m_inh_bank = 0;
}
}
m_inh_slot = i;
break;
}
}
}
// if no slots are inhibiting, make sure ROM is fully switched in
if ((m_inh_slot == -1) && (m_inh_bank != 0))
{
m_upperbank.select(0);
m_upperaux.select(0);
m_upper00.select(0);
m_upper01.select(0);
m_inh_bank = 0;
}
}
}
// FPI/CYA chip is connected to the VPB output of the 65816.
// this facilitates the documented behavior from the Firmware Reference.
u8 apple2gs_state::apple2gs_read_vector(offs_t offset)
{
// when IOLC shadowing is enabled, vector fetches always go to ROM,
// regardless of the language card config.
if (!(m_shadow & SHAD_IOLC))
{
return m_maincpu->space(AS_PROGRAM).read_byte(offset | 0xFFFFE0);
}
else // else vector fetches from bank 0 RAM
{
return m_maincpu->space(AS_PROGRAM).read_byte((offset & 0xffff) | 0xFFE0);
}
}
/***************************************************************************
START/RESET
***************************************************************************/
void apple2gs_state::machine_start()
{
m_ram_ptr = m_ram->pointer();
m_ram_size = m_ram->size();
m_speaker_state = 0;
m_speaker->level_w(m_speaker_state);
m_upperbank.select(0);
m_upperaux.select(0);
m_upper00.select(0);
m_upper01.select(0);
m_lcbank.select(0);
m_lcaux.select(0);
m_lc00.select(0);
m_lc01.select(0);
m_b0_0000bank.select(0);
m_e0_0000bank.select(0);
m_b0_0200bank.select(0);
m_e0_0200bank.select(0);
m_b0_0400bank.select(0);
m_e0_0400bank.select(0);
m_b0_0800bank.select(0);
m_e0_0800bank.select(0);
m_b0_2000bank.select(0);
m_e0_2000bank.select(0);
m_b0_4000bank.select(0);
m_e0_4000bank.select(0);
m_inh_bank = 0;
std::fill(std::begin(m_megaii_ram), std::end(m_megaii_ram), 0);
std::fill(std::begin(m_glu_regs), std::end(m_glu_regs), 0);
// setup speaker toggle volumes. this should be done mathematically probably,
// but these ad-hoc values aren't too bad.
#define LVL(x) (double(x) / 32768.0)
static const double lvlTable[16] =
{
LVL(0x0000), LVL(0x03ff), LVL(0x04ff), LVL(0x05ff), LVL(0x06ff), LVL(0x07ff), LVL(0x08ff), LVL(0x09ff),
LVL(0x0aff), LVL(0x0bff), LVL(0x0cff), LVL(0x0fff), LVL(0x1fff), LVL(0x3fff), LVL(0x5fff), LVL(0x7fff)
};
m_speaker->set_levels(16, lvlTable);
// precalculate joystick time constants
m_x_calibration = attotime::from_nsec(10800).as_double();
m_y_calibration = attotime::from_nsec(10800).as_double();
// cache slot devices
for (int i = 0; i <= 7; i++)
{
m_slotdevice[i] = m_a2bus->get_a2bus_card(i);
}
// setup video pointers
m_video->set_ram_pointers(m_megaii_ram, &m_megaii_ram[0x10000]);
m_video->set_char_pointer(memregion("gfx1")->base(), memregion("gfx1")->bytes());
m_video->setup_GS_graphics();
m_textcol = 0xf2;
m_video->set_GS_foreground((m_textcol >> 4) & 0xf);
m_video->set_GS_background(m_textcol & 0xf);
m_inh_slot = -1;
m_cnxx_slot = CNXX_UNCLAIMED;
// install memory beyond 256K
int ramsize = m_ram_size;
if (!m_is_rom3 && m_ram_size <= 1280 * 1024)
{
ramsize -= 0x40000; // subtract 256k for banks 0, 1, e0, e1
}
else if (m_is_rom3 || m_ram_size == 1024 * 1024 * 8)
{
ramsize -= 0x20000; // subtract 128K for banks 0 and 1, which are handled specially
}
if (ramsize)
{
address_space& space = m_maincpu->space(AS_PROGRAM);
// RAM sizes for both classes of machine no longer include the Mega II RAM
space.install_ram(0x020000, ramsize - 1 + 0x20000, m_ram_ptr + 0x020000);
}
// setup save states
save_item(NAME(m_speaker_state));
save_item(NAME(m_joystick_x1_time));
save_item(NAME(m_joystick_y1_time));
save_item(NAME(m_joystick_x2_time));
save_item(NAME(m_joystick_y2_time));
save_item(NAME(m_inh_slot));
save_item(NAME(m_inh_bank));
save_item(NAME(m_cnxx_slot));
save_item(NAME(m_romswitch));
save_item(NAME(m_an0));
save_item(NAME(m_an1));
save_item(NAME(m_an2));
save_item(NAME(m_an3));
save_item(NAME(m_intcxrom));
save_item(NAME(m_rombank));
save_item(NAME(m_slotc3rom));
save_item(NAME(m_altzp));
save_item(NAME(m_ramrd));
save_item(NAME(m_ramwrt));
save_item(NAME(m_ioudis));
save_item(NAME(m_vbl));
save_item(NAME(m_irqmask));
save_item(NAME(m_lcram));
save_item(NAME(m_lcram2));
save_item(NAME(m_lcprewrite));
save_item(NAME(m_lcwriteenable));
save_item(NAME(m_shadow));
save_item(NAME(m_speed));
save_item(NAME(m_textcol));
save_item(NAME(m_clock_control));
save_item(NAME(m_clkdata));
save_item(NAME(m_clock_frame));
save_item(NAME(m_motors_active));
save_item(NAME(m_slotromsel));
save_item(NAME(m_diskreg));
save_item(NAME(m_sndglu_ctrl));
save_item(NAME(m_sndglu_addr));
save_item(NAME(m_sndglu_dummy_read));
save_item(NAME(m_last_speed));
save_item(NAME(m_glu_regs));
save_item(NAME(m_glu_bus));
save_item(NAME(m_glu_mcu_read_kgs));
save_item(NAME(m_glu_816_read_dstat));
save_item(NAME(m_glu_mouse_read_stat));
save_item(NAME(m_glu_kbd_y));
save_item(NAME(m_intflag));
save_item(NAME(m_vgcint));
save_item(NAME(m_inten));
save_item(NAME(m_slot_irq));
save_item(NAME(m_slow_counter));
save_item(NAME(m_megaii_ram));
save_item(m_clkdata, "CLKDATA");
save_item(m_clock_control, "CLKCTRL");
save_item(NAME(m_adb_p2_last));
save_item(NAME(m_adb_p3_last));
save_item(NAME(m_adb_reset_freeze));
save_item(NAME(m_accel_unlocked));
save_item(NAME(m_accel_stage));
save_item(NAME(m_accel_fast));
save_item(NAME(m_accel_present));
save_item(NAME(m_accel_slotspk));
save_item(NAME(m_accel_gsxsettings));
save_item(NAME(m_accel_percent));
save_item(NAME(m_accel_temp_slowdown));
save_item(NAME(m_accel_speed));
save_item(NAME(m_motoroff_time));
}
void apple2gs_state::machine_reset()
{
m_adb_p2_last = m_adb_p3_last = 0;
m_adb_reset_freeze = 0;
m_romswitch = false;
m_video->page2_w(false);
m_video->set_GS_border(0x02);
m_video->set_GS_background(0x02);
m_video->set_GS_foreground(0x0f);
m_an0 = m_an1 = m_an2 = m_an3 = false;
m_gameio->an0_w(0);
m_gameio->an1_w(0);
m_gameio->an2_w(0);
m_gameio->an3_w(0);
m_vbl = false;
m_slotc3rom = false;
m_irqmask = 0;
m_intcxrom = false;
m_rombank = false;
m_video->a80store_w(false);
m_altzp = false;
m_ramrd = false;
m_ramwrt = false;
m_ioudis = true;
m_video->set_newvideo(0x01); // verified on ROM03 hardware
m_clock_frame = 0;
m_slot_irq = false;
m_clkdata = 0;
m_clock_control =0;
m_shadow = 0x00;
m_speed = 0x80;
m_motors_active = 0;
m_diskreg = 0;
m_intflag = 0;
m_vgcint = 0;
m_inten = 0;
m_motoroff_time = 0;
m_slow_counter = 0;
// always assert full speed on reset
m_maincpu->set_unscaled_clock(A2GS_14M/5);
m_last_speed = true;
m_sndglu_ctrl = 0;
m_sndglu_addr = 0;
m_sndglu_dummy_read = 0;
m_maincpu_space = &m_maincpu->space(AS_PROGRAM);
m_b0_0000bank.select(0);
m_e0_0000bank.select(0);
m_b0_0200bank.select(0);
m_e0_0200bank.select(0);
m_b0_0400bank.select(0);
m_e0_0400bank.select(0);
m_b0_0800bank.select(0);
m_e0_0800bank.select(0);
m_b0_2000bank.select(0);
m_e0_2000bank.select(0);
m_b0_4000bank.select(0);
m_e0_4000bank.select(0);
m_bank0_atc.select(1);
m_bank1_atc.select(1);
// LC default state: read ROM, write enabled, Dxxx bank 2
m_lcram = false;
m_lcram2 = true;
m_lcprewrite = false;
m_lcwriteenable = true;
// sync up the banking with the variables.
// RESEARCH: how does RESET affect LC state and aux banking states?
auxbank_update();
update_slotrom_banks();
// reset the slots
m_a2bus->reset_bus();
// with all the banking reset, now reset the CPU
m_maincpu->reset();
// Setup ZipGS
m_accel_unlocked = false;
m_accel_stage = 0;
m_accel_slotspk = 0x41; // speaker and slot 6 slow
m_accel_gsxsettings = 0;
m_accel_percent = 0; // 100% speed
m_accel_present = false;
m_accel_temp_slowdown = false;
m_accel_fast = false;
// is Zip enabled?
if (m_sysconfig->read() & 0x01)
{
static const int speeds[4] = { 7000000, 8000000, 12000000, 16000000 };
m_accel_present = true;
int idxSpeed = (m_sysconfig->read() >> 1);
m_accel_speed = speeds[idxSpeed];
m_accel_fast = true;
accel_full_speed();
}
}
void apple2gs_state::raise_irq(int irq)
{
if (!(m_irqmask & (1 << irq)))
{
m_irqmask |= (1 << irq);
//printf("raise IRQ %d (mask %x)\n", irq, m_irqmask);
if (m_irqmask)
{
m_intflag |= INTFLAG_IRQASSERTED;
m_maincpu->set_input_line(G65816_LINE_IRQ, ASSERT_LINE);
}
}
}
void apple2gs_state::lower_irq(int irq)
{
if (m_irqmask & (1 << irq))
{
m_irqmask &= ~(1 << irq);
//printf("lower IRQ %d (mask %x)\n", irq, m_irqmask);
if (!m_irqmask)
{
m_intflag &= ~INTFLAG_IRQASSERTED;
m_maincpu->set_input_line(G65816_LINE_IRQ, CLEAR_LINE);
}
else
{
m_maincpu->set_input_line(G65816_LINE_IRQ, ASSERT_LINE);
}
}
}
void apple2gs_state::update_speed()
{
bool isfast = false;
if (m_speed & SPEED_HIGH)
{
isfast = true;
}
if ((m_motors_active & (m_speed & 0x0f)) != 0)
{
isfast = false;
}
// prevent unnecessary reschedules by only setting this if it changed
if (isfast != m_last_speed)
{
if ((m_accel_present) && (isfast))
{
accel_full_speed();
}
else
{
m_maincpu->set_unscaled_clock(isfast ? A2GS_14M / 5 : A2GS_1M);
}
m_last_speed = isfast;
}
}
void apple2gs_state::accel_slot(int slot)
{
if ((m_accel_present) && (m_accel_slotspk & (1 << slot)))
{
m_accel_temp_slowdown = true;
m_acceltimer->adjust(attotime::from_msec(52));
accel_normal_speed();
}
}
TIMER_DEVICE_CALLBACK_MEMBER(apple2gs_state::accel_timer)