/
fmtowns.cpp
2884 lines (2625 loc) · 111 KB
/
fmtowns.cpp
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// license:BSD-3-Clause
// copyright-holders:Barry Rodewald
/*
Fujitsu FM-Towns
driver by Barry Rodewald
Japanese computer system released in 1989.
CPU: various AMD x86 CPUs, originally 80386DX (80387 available as an add-on).
later models use 80386SX, 80486 and Pentium CPUs
Sound: Yamaha YM3438 (some later models are use YMF276; Low voltage variation of YM3438, needs External DAC)
Ricoh RF5c68
CD-DA
Video: Custom
16 or 256 colours from a 24-bit palette, or 15-bit high-colour
1024 sprites (16x16), rendered direct to VRAM
16 colour text mode, rendered direct to VRAM
Later models add an unknown single channel 16-bit PCM/ADPCM (FreshTV, SJ, MX), and CL-GD543x Windows accelerator chipsets (SJ)
Fujitsu FM-Towns Marty
Japanese console, based on the FM-Towns computer, using an AMD 80386SX CPU,
released in 1993
Issues: Video emulation is far from complete.
*/
/*
Regular models:
Model | Form factor | CPU | Standard RAM | Max RAM | Standard FDDs | Standard HDD
FM Towns 1/2 | Tower | 386DX-16 | 1 MB (1) or 2 MB (2) | 6 MB | 1 or 2 | No SCSI controller
FM Towns 1F/2F/1H/2H | Tower | 386DX-16 | 1 MB (1F/1H) or 2 MB (2F/2H) | 8 MB | 1 (1F) or 2 (others) | 20 or 40 MB (H models only)
FM Towns 10F/20F/40H/80H | Tower | 386DX-16 | 2 MB | 26 MB | 1 (10F) or 2 (others) | 40 or 85 MB (H models only)
FM Towns II CX10/20/40/100 | Tower | 386DX-16 | 2 MB | 26 MB | 1 (CX10) or 2 (others) | No (CX10/20), 40 or 100 MB
FM Towns II UX10/20/40 | All-in-one | 386SX-16 | 2 MB | 10 MB | 1 (UX10) or 2 (others) | No (UX10/20) or 40 MB
FM Towns II HG20/40/100 | Desktop | 386DX-20 | 2 MB | 26 MB | 2 | No (HG20), 40 or 80 MB
FM Towns II HR20/100/200 | Desktop | 486SX-20 | 4 MB | 28 MB | 2 | No (HR20) 100 or 200 MB
FM Towns II UG10/20/40/80 | All-in-one | 386SX-20 | 2 MB | 10 MB | 1 (UG10) or 2 (others) | No (UG10/20), 40 or 80 MB
FM Towns II UR20/40/80 | All-in-one | 486SX-20 | 2 MB | 10 MB | 2 | No (UG20), 40 or 80 MB
FM Towns II ME20/170 | Desktop | 486SX-25 | 2 MB | 66 MB | 2 | No (ME20) or 170 MB
FM Towns II MA170/340 | Desktop | 486SX-33 | 4 MB | 100 MB | 2 | 170 or 340 MB
FM Towns II MX20/170/340 | Desktop | 486DX2-66 | 4 MB | 100 MB | 2 | No (MX20), 170 or 340 MB
FM Towns II Fresh/MF20/MF170W | Desktop | 486SX-33 | 4 MB (MF20) or 6 MB (others) | 68 MB | 2 | No (MF20), or 170 (others)
FM Towns II MA170W/MA340W | Desktop | 486SX-33 | 8 MB | 100 MB | 2 | 170 or 340 MB
FM Towns II MX170W/MA340W | Desktop | 486DX2-66 | 8 MB | 100 MB | 2 | 170 or 340 MB
FM Towns II Fresh-TV | Desktop | 486SX-33 | 6 MB | 68 MB | 2 | 170 MB
FM Towns II Fresh-E | Desktop | 486DX2-66 | 8 MB | 72 MB | 2 | 260 MB
FM Towns II Fresh-T | Desktop | 486SX-33 | 8 MB | 72 MB | 2 | 260 MB
FM Towns II EA2 | Desktop | 486SX-33 | 4 MB | 68 MB | 2 | No
FM Towns II HA2/HA53 | Desktop | 486DX2-66 | 4 MB (HA2) or 8 MB (HA53) | 100 MB | 2 | No (HA2) or 530 MB
FM Towns II HB2/HB53/HB53M | Desktop | Pentium-60 | 8 MB | 136 MB | 2 | No (HB2) or 530 MB
FM Towns II Fresh-ES/Fresh-ET | Desktop | 486DX2-66 | 8 MB | 72 MB | 1 | 360 MB
FM Towns II HC53/HC53M | Desktop | Pentium-90 | 8 MB | 136 MB | 1 | 540 MB
FM Towns II Fresh-FS/Fresh-FT | Desktop | 486DX4-100 | 8 MB | 72 MB | 1 | 540 MB
FM Towns Marty/Marty 2/TC Marty | Console | 386SX-16 | 2 MB | 4 MB | 1 | No SCSI controller
Car Marty | Car-mounted | 386SX-16 | 2 MB | ? | No | No SCSI controller
Education models:
Model | Form factor | CPU | Standard RAM | Max RAM | Standard FDDs | Standard HDD
FM Towns S1/S2 | Tower | 386DX-16 | 1 MB (S1) or 2 MB (S2) | 6 MB | 1 or 2 | No SCSI controller
FM Towns SF/SH | Tower | 386DX-16 | 1 MB (1F/1H) or 2 MB (2F/2H) | 8 MB | 2 | No (SF) or 40 MB
FM Towns SF2/SH2 | Tower | 386DX-16 | 2 MB | 26 MB | 2 | No (SF2) or 40 MB
FM Towns II SG20/40 | Desktop | 386DX-20 | 2 MB | 26 MB | 2 | No (SG20) or 40 MB
FM Towns II SR20/100 | Desktop | 486SX-20 | 4 MB | 28 MB | 2 | No (SR20) or 100 MB
FM Towns II SE | Desktop | 486SX-25 | 2 MB | 66 MB | 2 | No
FM Towns II SA | Desktop | 486SX-33 | 4 MB | 100 MB | 2 | No
FM Towns II SF20/SF170W | Desktop | 486SX-33 | 4 MB (SF20) or 6 MB (SF170W) | 100 MB | 2 | No (SF20) or 170 MB
FM Towns II SA170W | Desktop | 486SX-33 | 8 MB | 100 MB | 2 | 170 MB
FM Towns II SI2/SI26 | Desktop | 486SX-33 | 4 MB (SI2) or 8 MB (SI26) | 68 MB | 2 | No (SI2) or 260 MB
FM Towns II SJ2/SJ26 | Desktop | 486DX2-66 | 4 MB (SJ2) or 8 MB (SJ26) | 68 MB | 2 | No (SJ2) or 260 MB
FM Towns II SK53 | Desktop | Pentium-60 | 8 MB | 136 MB | 2 | 530 MB
FM Towns II SN | Laptop | 486DX2-66 | 4 MB | 36 MB | 1 | 340 MB
FM Towns II SJ2A/SJ53 | Desktop | 486DX2-66 | 4 MB (SJ2A) or 8 MB (SJ53) | 68 MB | 2 | No (SJ2A) or 530 MB
FM Towns II SL53 | Desktop | Pentium-90 | 8 MB | 136 MB | 2 | 530 MB
*/
/* I/O port map (incomplete, could well be incorrect too)
*
* 0x0000 : Master 8259 PIC
* 0x0002 : Master 8259 PIC
* 0x0010 : Slave 8259 PIC
* 0x0012 : Slave 8259 PIC
* 0x0020 RW: bit 0 = soft reset (read/write), bit 6 = power off (write), bit 7 = NMI vector protect
* 0x0022 W: bit 7 = power off (write)
* 0x0025 R : returns 0x00? (read)
* 0x0026 R : timer?
* 0x0028 RW: bit 0 = NMI mask (read/write)
* 0x0030 R : Machine ID (low)
* 0x0031 R : Machine ID (high)
* 0x0032 RW: bit 7 = RESET, bit 6 = CLK, bit 0 = data (serial ROM)
* 0x0040 : 8253 PIT counter 0
* 0x0042 : 8253 PIT counter 1
* 0x0044 : 8253 PIT counter 2
* 0x0046 : 8253 PIT mode port
* 0x0060 : 8253 PIT timer control
* 0x006c RW: returns 0x00? (read) timer? (write)
* 0x00a0-af: DMA controller 1 (uPD71071)
* 0x00b0-bf: DMA controller 2 (uPD71071)
* 0x0200-0f: Floppy controller (MB8877A)
* 0x0400 : Video / CRTC (unknown)
* 0x0404 : Disable VRAM, CMOS, memory-mapped I/O (everything in low memory except the BIOS)
* 0x0440-5f: Video / CRTC
* 0x0480 RW: bit 1 = disable BIOS ROM
* 0x048a RW: JEIDA v3/v4(?) IC Memory card status
* 0x0490 RW: JEIDA v4 IC Memory card page select
* 0x0491 RW: JEIDA v4 IC Memory card
* 0x04c0-cf: CD-ROM controller
* 0x04d5 : Sound mute
* 0x04d8 : YM3438 control port A / status
* 0x04da : YM3438 data port A / status
* 0x04dc : YM3438 control port B / status
* 0x04de : YM3438 data port B / status
* 0x04e0-e3: volume ports
* 0x04e9-ec: IRQ masks
* 0x04f0-f8: RF5c68 registers
* 0x05e8 R : RAM size in MB
* 0x05ec RW: bit 0 = compatibility mode?
* 0x0600 RW: Keyboard data port (8042)
* 0x0602 : Keyboard control port (8042)
* 0x0604 : (8042)
* 0x0a00-0a: RS-232C interface (i8251)
* 0x3000 - 0x3fff : CMOS RAM
* 0xfd90-a0: CRTC / Video
* 0xff81: CRTC / Video - returns value in RAM location 0xcff81?
*
* IRQ list
*
* IRQ0 - PIT Timer IRQ
* IRQ1 - Keyboard
* IRQ2 - Serial Port
* IRQ6 - Floppy Disc Drive
* IRQ7 - PIC Cascade IRQ
* IRQ8 - SCSI controller
* IRQ9 - Built-in CD-ROM controller
* IRQ11 - VSync interrupt
* IRQ12 - Printer port
* IRQ13 - Sound (YM3438/RF5c68), Mouse
* IRQ15 - 16-bit PCM (expansion?)
*
* Machine ID list (I/O port 0x31)
*
1(01h) FM-TOWNS 1/2
2(02h) FM-TOWNS 1F/2F/1H/2H
3(03h) FM-TOWNS 10F/20F/40H/80H
4(04h) FM-TOWNSII UX
5(05h) FM-TOWNSII CX
6(06h) FM-TOWNSII UG
7(07h) FM-TOWNSII HR
8(08h) FM-TOWNSII HG
9(09h) FM-TOWNSII UR
11(0Bh) FM-TOWNSII MA
12(0Ch) FM-TOWNSII MX
13(0Dh) FM-TOWNSII ME
14(0Eh) TOWNS Application Card (PS/V Vision)
15(0Fh) FM-TOWNSII MF/Fresh/Fresh???TV
16(10h) FM-TOWNSII SN
17(11h) FM-TOWNSII HA/HB/HC
19(13h) FM-TOWNSII EA/Fresh???T/Fresh???ET/Fresh???FT
20(14h) FM-TOWNSII Fresh???E/Fresh???ES/Fresh???FS
22(16h) FMV-TOWNS H/Fresh???GS/Fresh???GT/H2
23(17h) FMV-TOWNS H20
74(4Ah) FM-TOWNS MARTY
*/
/*
Fujitsu FM Towns Marty
PCB Layout
----------
CA20142-B21X
CN10 CN1
|-| |-| |-| |----------------------|
|--| |-| |-| |----|-|-------------|----------------------|------------|
|14577 CN11 SW2 |--------| MROM.M37|--------| |
|14576 TMS48C121DZ-80 |FUJITSU | |FUJITSU | |
| TMS48C121DZ-80 |CG24243 | |CS10501 | |
|MB40968 TMS48C121DZ-80 |(QFP208)| MROM.M36|(QFP160)| |
||--------| TMS48C121DZ-80 |--------| |--------| 62256 |
||FUJITSU | HM511664JP8 CN12 FUJITSU |
||CE31755 | 8451 (DIP8) |
||(QFP160)| |
||--------| 4.9152MHz |
|CN13 |--------| 28.63636MHz |-|
| |FUJITSU | |----------------------|
| RTC58323 |CG31553 | | |
|BATTERY |(QFP208)| 32MHz 74LS00 | |
| |--------| |------| | CN2 |
| LC7881 MB84256 |I386SX| | PCMCIA SLOT |
| TL084 CN4 | -16 | | |
||--------| |------| | |
||FUJITSU | MB814400A-70PZ | |
||CS09501 | MB814400A-70PZ |----------------------|
||(QFP120)| MB814400A-70PZ |--------|74LS14 74HC08 |-|
||--------| MB814400A-70PZ | RICOH | 3771 |
| YM3438 |RU6101MF| |
|4560 MB81C78 |(QFP44) | |
| MB88505 |------| |--------| |
| CN3 |YM6063| LED2 LED1 LED3 |
|CN9 CN8 VOL |(QFP80| CN5 CN6 SW1 CN7|
|---------------------|------|----------------------------------------|
Notes:
All IC's shown.
Main CPU Intel 80386SX-16 running at 16.000MHz
CN1 - Multi-pin connector possibly for cartridge or external peripheral connector?
CN2 - PCMCIA slot
CN3 - 24 pin connector for ?
CN4 - CDROM connector? (multi-pin connector with internal slot for a thin cable)
CN5/6 - DB9 connectors (joystick ports?)
CN7 - Power input socket
CN8/9 - Headphone out jacks?
CN10 - Header with left/right RCA audio jacks and composite video output
CN11 - S-VIDEO output
CN12 - 8 pin connector (possibly power related for the CDROM?)
CN13 - 2 pin connector (fan power?)
SW1 - Reset Switch?
SW2 - 2 position slide switch
MROM* - Hitachi HN624116 16MBit SOP44 maskROM
*/
#include "emu.h"
#include "fmtowns.h"
#include "bus/scsi/scsi.h"
#include "bus/scsi/scsihd.h"
#include "screen.h"
#include "softlist.h"
#include "speaker.h"
#include <math.h>
#define LOG_SYS (1U << 1)
#define LOG_CD (1U << 2)
#define LOG_CD_UNKNOWN (1U << 3)
#define VERBOSE (LOG_GENERAL | LOG_CD_UNKNOWN)
#include "logmacro.h"
// CD controller IRQ types
#define TOWNS_CD_IRQ_MPU 1
#define TOWNS_CD_IRQ_DMA 2
enum
{
MOUSE_START,
MOUSE_SYNC,
MOUSE_X_HIGH,
MOUSE_X_LOW,
MOUSE_Y_HIGH,
MOUSE_Y_LOW
};
inline uint8_t towns_state::byte_to_bcd(uint8_t val)
{
return ((val / 10) << 4) | (val % 10);
}
inline uint8_t towns_state::bcd_to_byte(uint8_t val)
{
return (((val & 0xf0) >> 4) * 10) + (val & 0x0f);
}
inline uint32_t towns_state::msf_to_lbafm(uint32_t val) // because the CDROM core doesn't provide this
{
uint8_t m,s,f;
f = bcd_to_byte(val & 0x0000ff);
s = (bcd_to_byte((val & 0x00ff00) >> 8));
m = (bcd_to_byte((val & 0xff0000) >> 16));
return ((m * (60 * 75)) + (s * 75) + f) - 150;
}
void towns_state::init_serial_rom()
{
// TODO: init serial ROM contents
int x;
static const uint8_t code[8] = { 0x04,0x65,0x54,0xA4,0x95,0x45,0x35,0x5F };
uint8_t* srom = nullptr;
if(m_serial)
srom = m_serial->base();
memset(m_towns_serial_rom.get(),0,256/8);
if(srom)
{
memcpy(m_towns_serial_rom.get(),srom,32);
m_towns_machine_id = (m_towns_serial_rom[0x18] << 8) | m_towns_serial_rom[0x17];
logerror("Machine ID in serial ROM: %04x\n",m_towns_machine_id);
return;
}
for(x=8;x<=21;x++)
m_towns_serial_rom[x] = 0xff;
for(x=0;x<=7;x++)
{
m_towns_serial_rom[x] = code[x];
}
// add Machine ID
m_towns_machine_id = 0x0101;
m_towns_serial_rom[0x17] = 0x01;
m_towns_serial_rom[0x18] = 0x01;
// serial number?
m_towns_serial_rom[29] = 0x10;
m_towns_serial_rom[28] = 0x6e;
m_towns_serial_rom[27] = 0x54;
m_towns_serial_rom[26] = 0x32;
m_towns_serial_rom[25] = 0x10;
}
uint8_t towns_state::towns_system_r(offs_t offset)
{
uint8_t ret = 0;
switch(offset)
{
case 0x00:
LOGMASKED(LOG_SYS, "SYS: port 0x20 read\n");
return 0x00;
case 0x05:
LOGMASKED(LOG_SYS, "SYS: port 0x25 read\n");
return 0x00;
/* case 0x06:
count = (m_towns_freerun_counter->elapsed() * ATTOSECONDS_TO_HZ(ATTOSECONDS_IN_USEC(1))).as_double();
return count & 0xff;
case 0x07:
count = (m_towns_freerun_counter->elapsed() * ATTOSECONDS_TO_HZ(ATTOSECONDS_IN_USEC(1))).as_double();
return (count >> 8) & 0xff;
*/ case 0x06:
//LOGMASKED(LOG_SYS, "SYS: (0x26) timer read\n");
return m_freerun_timer;
case 0x07:
return m_freerun_timer >> 8;
case 0x08:
//LOGMASKED(LOG_SYS, "SYS: (0x28) NMI mask read\n");
return m_nmi_mask & 0x01;
case 0x10:
LOGMASKED(LOG_SYS, "SYS: (0x30) Machine ID read\n");
return (m_towns_machine_id >> 8) & 0xff;
case 0x11:
LOGMASKED(LOG_SYS, "SYS: (0x31) Machine ID read\n");
return m_towns_machine_id & 0xff;
case 0x12:
/* Bit 0 = data, bit 6 = CLK, bit 7 = RESET, bit 5 is always 1? */
ret = (m_towns_serial_rom[m_towns_srom_position/8] & (1 << (m_towns_srom_position%8))) ? 1 : 0;
ret |= m_towns_srom_clk;
ret |= m_towns_srom_reset;
//LOGMASKED(LOG_SYS, "SYS: (0x32) Serial ROM read [0x%02x, pos=%i]\n",ret,towns_srom_position);
return ret;
default:
//LOGMASKED(LOG_SYS, "SYS: Unknown system port read (0x%02x)\n",offset+0x20);
return 0x00;
}
}
void towns_state::towns_system_w(offs_t offset, uint8_t data)
{
switch(offset)
{
case 0x00: // bit 7 = NMI vector protect, bit 6 = power off, bit 0 = software reset, bit 3 = A20 line?
// space.m_maincpu->set_input_line(INPUT_LINE_A20,(data & 0x08) ? CLEAR_LINE : ASSERT_LINE);
LOGMASKED(LOG_SYS, "SYS: port 0x20 write %02x\n",data);
break;
case 0x02:
LOGMASKED(LOG_SYS, "SYS: (0x22) power port write %02x\n",data);
break;
case 0x08:
//LOGMASKED(LOG_SYS, "SYS: (0x28) NMI mask write %02x\n",data);
m_nmi_mask = data & 0x01;
break;
case 0x12:
//LOGMASKED(LOG_SYS, "SYS: (0x32) Serial ROM write %02x\n",data);
// clocks on low-to-high transition
if((data & 0x40) && m_towns_srom_clk == 0) // CLK
{ // advance to next bit
m_towns_srom_position++;
}
if((data & 0x80) && m_towns_srom_reset == 0) // reset
{ // reset to beginning
m_towns_srom_position = 0;
}
m_towns_srom_clk = data & 0x40;
m_towns_srom_reset = data & 0x80;
break;
default:
LOGMASKED(LOG_SYS, "SYS: Unknown system port write 0x%02x (0x%02x)\n",data,offset);
break;
}
}
void towns_state::towns_intervaltimer2_w(offs_t offset, uint8_t data)
{
switch(offset)
{
case 0x00:
m_intervaltimer2_irqmask = data & 0x80;
break;
case 0x02:
m_intervaltimer2_period = (m_intervaltimer2_period & 0xff00) | data;
popmessage("Interval Timer 2 period changed to %04x",m_intervaltimer2_period);
break;
case 0x03:
m_intervaltimer2_period = (data << 8) | (m_intervaltimer2_period & 0x00ff);
popmessage("Interval Timer 2 period changed to %04x",m_intervaltimer2_period);
break;
}
}
uint8_t towns_state::towns_intervaltimer2_r(offs_t offset)
{
uint8_t ret = 0;
switch(offset)
{
case 0x00:
if(m_intervaltimer2_timeout_flag != 0)
ret |= 0x40;
if(m_intervaltimer2_irqmask != 0)
ret |= 0x80;
m_intervaltimer2_timeout_flag = 0; // flag reset on read
return ret;
case 0x02:
return m_intervaltimer2_period & 0x00ff;
case 0x03:
return m_intervaltimer2_period >> 8;
}
return 0xff;
}
TIMER_CALLBACK_MEMBER(towns_state::freerun_inc)
{
m_freerun_timer++;
}
TIMER_CALLBACK_MEMBER(towns_state::intervaltimer2_timeout)
{
m_intervaltimer2_timeout_flag = 1;
}
TIMER_CALLBACK_MEMBER(towns_state::wait_end)
{
m_maincpu->set_input_line(INPUT_LINE_HALT,CLEAR_LINE);
}
uint8_t towns_state::towns_sys6c_r()
{
LOGMASKED(LOG_SYS, "SYS: (0x6c) Timer? read\n");
return 0x00;
}
void towns_state::towns_sys6c_w(uint8_t data)
{
// halts the CPU for 1 microsecond
m_maincpu->set_input_line(INPUT_LINE_HALT,ASSERT_LINE);
m_towns_wait_timer->adjust(attotime::from_usec(1),0,attotime::never);
}
template<int Chip>
uint8_t towns_state::towns_dma_r(offs_t offset)
{
logerror("DMA#%01x: read register %i\n",Chip,offset);
return m_dma[Chip]->read(offset);
}
template<int Chip>
void towns_state::towns_dma_w(offs_t offset, uint8_t data)
{
logerror("DMA#%01x: wrote 0x%02x to register %i\n",Chip,data,offset);
m_dma[Chip]->write(offset, data);
}
/*
* Floppy Disc Controller (MB8877A)
*/
void towns_state::mb8877a_irq_w(int state)
{
if(m_towns_fdc_irq6mask == 0)
state = 0;
m_pic_master->ir6_w(state); // IRQ6 = FDC
if(IRQ_LOG) logerror("PIC: IRQ6 (FDC) set to %i\n",state);
}
void towns_state::mb8877a_drq_w(int state)
{
m_dma[0]->dmarq(state, 0);
}
uint8_t towns_state::towns_floppy_r(offs_t offset)
{
uint8_t ret;
switch(offset)
{
case 0x00:
return m_fdc->status_r();
case 0x02:
return m_fdc->track_r();
case 0x04:
return m_fdc->sector_r();
case 0x06:
return m_fdc->data_r();
case 0x08: // selected drive status?
//logerror("FDC: read from offset 0x08\n");
ret = 0x80; // always set
switch(m_towns_selected_drive)
{
case 1:
ret |= 0x0c;
if(m_flop[0]->get_device() && m_flop[0]->get_device()->exists())
ret |= 0x03;
break;
case 2:
ret |= 0x0c;
if(m_flop[1]->get_device() && m_flop[1]->get_device()->exists())
ret |= 0x03;
break;
case 3:
case 4:
case 0:
default:
break;
}
return ret;
case 0x0e: // DRVCHG
logerror("FDC: read from offset 0x0e\n");
if(m_towns_selected_drive == 1)
if (m_flop[0]->get_device())
return m_flop[0]->get_device()->dskchg_r();
if(m_towns_selected_drive == 2)
if (m_flop[1]->get_device())
return m_flop[1]->get_device()->dskchg_r();
return 0x00;
default:
logerror("FDC: read from invalid or unimplemented register %02x\n",offset);
}
return 0xff;
}
void towns_state::towns_floppy_w(offs_t offset, uint8_t data)
{
floppy_image_device* sel[4] = { m_flop[0]->get_device(), m_flop[1]->get_device(), nullptr, nullptr };
switch(offset)
{
case 0x00:
// Commands 0xd0 and 0xfe (Write Track) are apparently ignored?
if(data == 0xd0)
return;
if(data == 0xfe)
return;
m_fdc->cmd_w(data);
logerror("FDC: Command %02x\n",data);
break;
case 0x02:
m_fdc->track_w(data);
logerror("FDC: Track %02x\n",data);
break;
case 0x04:
m_fdc->sector_w(data);
logerror("FDC: Sector %02x\n",data);
break;
case 0x06:
m_fdc->data_w(data);
logerror("FDC: Data %02x\n",data);
break;
case 0x08:
{
// bit 5 - CLKSEL
// docs are unclear about this but there's only one motor control line and turning on only the selected drive doesn't work properly.
for(int i = 0; i < 4; i++)
{
if(sel[i] != nullptr)
{
sel[i]->mon_w((~data & 0x10)>>4);
sel[i]->ss_w((data & 0x04)>>2);
}
}
m_fdc->dden_w(BIT(~data, 1));
m_towns_fdc_irq6mask = data & 0x01;
//logerror("FDC: Config drive%i %02x\n",m_towns_selected_drive-1,data);
break;
}
case 0x0c: // drive select
switch(data & 0x0f)
{
case 0x00:
m_towns_selected_drive = 0; // No drive selected
break;
case 0x01:
m_towns_selected_drive = 1;
if(sel[0] != nullptr)
m_fdc->set_floppy(sel[0]);
break;
case 0x02:
m_towns_selected_drive = 2;
if(sel[1] != nullptr)
m_fdc->set_floppy(sel[1]);
break;
case 0x04:
m_towns_selected_drive = 3;
if(sel[2] != nullptr)
m_fdc->set_floppy(sel[2]);
break;
case 0x08:
m_towns_selected_drive = 4;
if(sel[3] != nullptr)
m_fdc->set_floppy(sel[3]);
break;
}
//logerror("FDC: drive select %02x\n",data);
break;
default:
logerror("FDC: write %02x to invalid or unimplemented register %02x\n",data,offset);
}
}
uint16_t towns_state::towns_fdc_dma_r()
{ uint16_t data = m_fdc->data_r();
return data;
}
void towns_state::towns_fdc_dma_w(uint16_t data)
{
m_fdc->data_w(data);
}
/*
* Port 0x600-0x607 - Keyboard controller (8042 MCU)
*
* Sends two-byte code on each key press and release.
* First byte has the MSB set, and contains shift/ctrl/keyboard type flags
* Known bits:
* bit 7 = always 1
* bits 6-5 = keyboard type
* 00 = thumb shift (NICOLA) keyboard
* 01 = JIS keyboard
* 10 = new JIS keyboard (with ALT key?)
* 11 = extended use (?)
* bit 4 = key release
* bit 3 = ctrl
* bit 2 = shift
* bit 1 = left shift (thumb shift only)
* bit 0 = right shift (thumb shift only)
*
* Second byte has the MSB reset, and contains the scancode of the key
* pressed or released.
* bit 7 = always 0
* bits 6-0 = key scancode
*/
void towns_state::kb_sendcode(uint8_t scancode, int release)
{
switch(release)
{
case 0: // key press
m_towns_kb_output = 0xc0;
m_towns_kb_extend = scancode & 0x7f;
if (m_kb_ports[2]->read() & 0x00080000)
m_towns_kb_output |= 0x04;
if (m_kb_ports[2]->read() & 0x00040000)
m_towns_kb_output |= 0x08;
break;
case 1: // key release
m_towns_kb_output = 0xd0;
m_towns_kb_extend = scancode & 0x7f;
if (m_kb_ports[2]->read() & 0x00080000)
m_towns_kb_output |= 0x04;
if (m_kb_ports[2]->read() & 0x00040000)
m_towns_kb_output |= 0x08;
break;
case 2: // extended byte
m_towns_kb_output = scancode;
m_towns_kb_extend = 0xff;
break;
}
m_towns_kb_status |= 0x01;
if(m_towns_kb_irq1_enable)
{
m_pic_master->ir1_w(1);
if(IRQ_LOG) logerror("PIC: IRQ1 (keyboard) set high\n");
}
//logerror("KB: sending scancode 0x%02x\n",scancode);
}
TIMER_CALLBACK_MEMBER(towns_state::poll_keyboard)
{
uint8_t scan = 0;
for(int port = 0; port < 4; port++)
{
uint32_t portval = m_kb_ports[port]->read();
for(int bit = 0; bit < 32; bit++)
{
if(BIT(portval, bit) != BIT(m_kb_prev[port], bit))
{ // bit changed
if(BIT(portval, bit) == 0) // release
kb_sendcode(scan, 1);
else
kb_sendcode(scan, 0);
}
scan++;
}
m_kb_prev[port] = portval;
}
}
uint8_t towns_state::towns_keyboard_r(offs_t offset)
{
uint8_t ret = 0x00;
switch(offset)
{
case 0: // scancode output
ret = m_towns_kb_output;
//logerror("KB: read keyboard output port, returning %02x\n",ret);
m_pic_master->ir1_w(0);
if(IRQ_LOG) logerror("PIC: IRQ1 (keyboard) set low\n");
if(m_towns_kb_extend != 0xff)
{
kb_sendcode(m_towns_kb_extend,2);
}
else
m_towns_kb_status &= ~0x01;
return ret;
case 1: // status
//logerror("KB: read status port, returning %02x\n",m_towns_kb_status);
return m_towns_kb_status;
default:
logerror("KB: read offset %02x\n",offset);
}
return 0x00;
}
void towns_state::towns_keyboard_w(offs_t offset, uint8_t data)
{
switch(offset)
{
case 0: // command input
m_towns_kb_status &= ~0x08;
m_towns_kb_status |= 0x01;
break;
case 1: // control
m_towns_kb_status |= 0x08;
break;
case 2: // IRQ1 enable
m_towns_kb_irq1_enable = data & 0x01;
break;
default:
logerror("KB: wrote 0x%02x to offset %02x\n",data,offset);
}
}
/*
* Port 0x60 - PIT Timer control
* On read: bit 0: Timer 0 output level
* bit 1: Timer 1 output level
* bits 4-2: Timer masks (timer 2 = beeper)
* On write: bits 2-0: Timer mask set
* bit 7: Timer 0 output reset
*/
uint8_t towns_state::speaker_get_spk()
{
return m_towns_spkrdata & m_pit_out2;
}
void towns_state::speaker_set_spkrdata(uint8_t data)
{
m_towns_spkrdata = data ? 1 : 0;
m_speaker->level_w(speaker_get_spk());
}
uint8_t towns_state::towns_port60_r()
{
uint8_t val = 0x00;
if (m_pit_out0)
val |= 0x01;
if (m_pit_out1)
val |= 0x02;
val |= (m_towns_timer_mask & 0x07) << 2;
//logerror("PIT: port 0x60 read, returning 0x%02x\n",val);
return val;
}
void towns_state::towns_port60_w(uint8_t data)
{
if(data & 0x80)
{
//towns_pic_irq(dev,0);
m_timer0 = 0;
m_pic_master->ir0_w(m_timer0 || m_timer1);
}
m_towns_timer_mask = data & 0x07;
speaker_set_spkrdata(data & 0x04);
//logerror("PIT: wrote 0x%02x to port 0x60\n",data);
}
uint8_t towns_state::towns_sys5e8_r(offs_t offset)
{
switch(offset)
{
case 0x00:
LOGMASKED(LOG_SYS, "SYS: read RAM size port (%i)\n",m_ram->size());
return m_ram->size()/1048576;
case 0x02:
LOGMASKED(LOG_SYS, "SYS: read port 5ec\n");
return m_compat_mode & 0x01;
}
return 0x00;
}
void towns_state::towns_sys5e8_w(offs_t offset, uint8_t data)
{
switch(offset)
{
case 0x00:
LOGMASKED(LOG_SYS, "SYS: wrote 0x%02x to port 5e8\n",data);
break;
case 0x02:
LOGMASKED(LOG_SYS, "SYS: wrote 0x%02x to port 5ec\n",data);
m_compat_mode = data & 0x01;
break;
}
}
// Sound/LED control (I/O port 0x4e8-0x4ef)
// R/O -- (0x4e9) FM IRQ flag (bit 0), PCM IRQ flag (bit 3)
// (0x4ea) PCM IRQ mask
// R/W -- (0x4eb) PCM IRQ flag
// W/O -- (0x4ec) LED control
uint8_t towns_state::towns_sound_ctrl_r(offs_t offset)
{
uint8_t ret = 0;
switch(offset)
{
case 0x00:
ret = 1;
break;
case 0x01:
if(m_towns_fm_irq_flag)
ret |= 0x01;
if(m_towns_pcm_irq_flag)
ret |= 0x08;
break;
case 0x02:
ret = m_towns_pcm_channel_mask;
break;
case 0x03:
ret = m_towns_pcm_channel_flag;
m_towns_pcm_channel_flag = 0;
m_towns_pcm_irq_flag = 0;
if(m_towns_fm_irq_flag == 0)
{
m_pic_slave->ir5_w(0);
if(IRQ_LOG) logerror("PIC: IRQ13 (PCM) set low\n");
}
break;
// default:
//logerror("FM: unimplemented port 0x%04x read\n",offset + 0x4e8);
}
return ret;
}
void towns_state::towns_sound_ctrl_w(offs_t offset, uint8_t data)
{
switch(offset)
{
case 0x02: // PCM channel interrupt mask
m_towns_pcm_channel_mask = data;
break;
default:
logerror("FM: unimplemented port 0x%04x write %02x\n",offset + 0x4e8,data);
}
}
// Controller ports
// Joysticks are multiplexed, with fire buttons available when bits 0 and 1 of port 0x4d6 are high. (bits 2 and 3 for second port)
uint8_t towns_state::towns_padport_r(offs_t offset)
{
// Documentation indicates bit 7 is unused and should be ignored.
// Tatsujin Ou expects it to read as zero to navigate menus.
// Unclear whether it always reads as zero, or it's affected by something undocumented.
unsigned const pad = BIT(offset, 1);
return m_pad_ports[pad]->read() & (0x0f | (bitswap<3>(m_towns_pad_mask, pad + 4, (pad * 2) + 1, pad * 2) << 4));
}
void towns_state::towns_pad_mask_w(uint8_t data)
{
m_towns_pad_mask = data;
m_pad_ports[0]->pin_6_w(BIT(data, 0));
m_pad_ports[0]->pin_7_w(BIT(data, 1));
m_pad_ports[0]->pin_8_w(BIT(data, 4));
m_pad_ports[1]->pin_6_w(BIT(data, 2));
m_pad_ports[1]->pin_7_w(BIT(data, 3));
m_pad_ports[1]->pin_8_w(BIT(data, 5));
}
uint8_t towns_state::towns_cmos_low_r(offs_t offset)
{
if(m_towns_mainmem_enable != 0)
return m_ram->pointer()[offset + 0xd8000];
if(m_nvram)
return m_nvram[offset >> 2] >> ((offset & 3) << 3);
else
return m_nvram16[offset >> 1] >> ((offset & 1) << 3);
}
void towns_state::towns_cmos_low_w(offs_t offset, uint8_t data)
{
if(m_towns_mainmem_enable != 0)
m_ram->pointer()[offset+0xd8000] = data;
else
if(m_nvram)
{
uint8_t shift = (offset & 3) << 3;
m_nvram[offset >> 2] &= ~(0xff << shift);
m_nvram[offset >> 2] |= (uint32_t)data << shift;
}
else
{
uint8_t shift = (offset & 1) << 3;
m_nvram16[offset >> 1] &= ~(0xff << shift);
m_nvram16[offset >> 1] |= (uint16_t)data << shift;
}
}
uint8_t towns_state::towns_cmos_r(offs_t offset)
{
if(m_nvram)
return m_nvram[offset >> 2] >> ((offset & 3) << 3);
else
return m_nvram16[offset >> 1] >> ((offset & 1) << 3);
}
void towns_state::towns_cmos_w(offs_t offset, uint8_t data)
{
if(m_nvram)
{
uint8_t shift = (offset & 3) << 3;
m_nvram[offset >> 2] &= ~(0xff << shift);
m_nvram[offset >> 2] |= (uint32_t)data << shift;
}
else
{
uint8_t shift = (offset & 1) << 3;
m_nvram16[offset >> 1] &= ~(0xff << shift);
m_nvram16[offset >> 1] |= (uint16_t)data << shift;
}
}
void towns_state::towns_update_video_banks()
{
uint8_t* ROM = m_user->base();
if(m_towns_mainmem_enable != 0) // first MB is RAM
{
// membank(1)->set_base(m_ram->pointer()+0xc0000);
// membank(2)->set_base(m_ram->pointer()+0xc8000);
// membank(3)->set_base(m_ram->pointer()+0xc9000);
// membank(4)->set_base(m_ram->pointer()+0xca000);
// membank(5)->set_base(m_ram->pointer()+0xca000);
// membank(10)->set_base(m_ram->pointer()+0xca800);
m_bank_cb000_r->set_base(m_ram->pointer()+0xcb000);
m_bank_cb000_w->set_base(m_ram->pointer()+0xcb000);
if(m_towns_system_port & 0x02)
m_bank_f8000_r->set_base(m_ram->pointer()+0xf8000);
else
m_bank_f8000_r->set_base(ROM+0x238000);
m_bank_f8000_w->set_base(m_ram->pointer()+0xf8000);
return;
}
else // enable I/O ports and VRAM
{