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itech32.cpp
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itech32.cpp
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// license:BSD-3-Clause
// copyright-holders:Aaron Giles, Brian Troha
/***************************************************************************
Incredible Technologies/Strata system
(32-bit blitter variant)
Driver by Aaron Giles
Golden Tee variants & World Class Bowling Deluxe additions by Brian A. Troha
Games supported:
* Time Killers (7 sets)
* Bloodstorm (5 sets)
* Hard Yardage (3 sets)
* Pairs (4 sets)
* Pairs Redemption (Child's version of pairs)
* Driver's Edge (1 set)
* World Class Bowling (14 sets)
* Street Fighter: The Movie (5 sets)
* Shuffleshot (5 sets)
* Golden Tee 3D Golf (12 sets)
* Golden Tee Golf '97 (7 sets)
* Golden Tee Golf '98 (7 sets)
* Golden Tee Golf '99 (4 sets)
* Golden Tee Golf 2K (5 sets)
* Golden Tee Classic (3 sets)
* Must Shoot TV (prototype) (1 set)
* Power Up Baseball (prototype) (1 set)
Known issues:
* volume controls do not work in the Golden Tee games
* Driver's Edge accesses many uninitialized RAM locations;
requires hack to make steering in attract mode work
* available PIC dumps aren't hooked up
NOTE: The Japanese World Class Bowling v1.3 set reads the trackball
at a 45 degree offset from standard orientation. This is NOT a
bug and is not controlled via dipswitches like some GT3D sets
****************************************************************************
There are at least 4 types of Golden Tee PCBs
* 3 Tier long ROM board
- Versions end in "L"
- No cocktail mode
- 2 trackball connectors
- GT3D
* 3 Tier short ROM board
- Versions end in "S"
- No cocktail mode
- 2 trackball connectors
- GT3D
* 3 Tier short ROM board
- Versions end in "S"
- No cocktail mode
- 1 trackball connector
- GT97 through Classic
* Large single layer PCB
- GT3D for this board ends in "N" for "Non-Tournament"
- Tournament versions end in "T" (requires optional chips, see below)
- 2 trackball connectors
- Cocktail mode support with most recent version of each chipset, except GT3D
- GT3D through GT Classic
There are at least 3 different revisions of the sound board for the 3-tier Golden Tee boards
P/N 1066 Rev 2: Ensoniq sample 2M 1350901601, sound CPU code is V1.0 to V1.2
P/N 1078 Rev 1: Ensoniq sample 2MX16U 1350901801, sound CPU code is V2.0 to V2.2
P/N 1078 Rev 1: This revision dropped the Ensoniq samples and converted to the samples
currently used on the single PCB format. ROMs are identified by the use of "NR"
on the label and the sound code is labeled "GTG3_NR(U23)"
GT Classic was the last chipset for this platform and was sold mainly as an upgrade for GT99/GT2K
Later versions of games (Golden Tee Golf, Shuffle Shot & World Class
Bowling) converged to a single platform, the large single PCB
(P/N 1083 Rev 2). With the correct jumpers setting (surface mounted)
and chipset this board can run any of the 3 listed programs.
Starting with GT Fore!, I.T. moved to a redesigned hardware platform known as the Eagle platform.
It has a main board with a 3Dfx video card and is hard drive based. This series started with
GT Fore! in 2000 and continued through 2006 ending with Golden Tee Complete. This final
version included all the courses from all the previous years in the Fore! series.
The Eagle platform also supports I.T.'s hunting series "Big Buck Hunter", the light game gun
called Carnival King as well as the limited release game Virtual Pool.
Some time in 2004 I.T. introduced a new bowling game called Silver Strike Bowling on a full
blown PC system known as "Nighthawk System Box" (AKA The Nighthawk Chassis) to replace it's
aging World Class Bowling game. Other known games on this platform include Golden Tee Live!,
Power Putt Golf (Mini-Golf) and Target Toss Pro: Lawn Darts / Bags
Trivia: For the Golden Tee series, the second generation was called GT2. The third gen was known
as GT3 but also included Golden Tee '97 through 2K and Classic. The fourth gen on the
Eagle platform was GT4... using the pun or play on words became the GT Fore! series ;-)
****************************************************************************
Memory map TBD
****************************************************************************
Memory sizes:
Time Killers:
2 * MS6264L = 2 * 8k = 16k (main RAM)
6 * V52C8126K = 6 * 128k = 768k (video RAM)
3 * NMS64X8AM = 3 * 32k = 96k (palette RAM)
Hard Yardage:
2 * MS62256 = 2 * 32k = 64k (main RAM)
4 * V52C8128K = 4 * 128k = 512k (video RAM)
3 * MB84256 = 3 * 32k = 96k (palette RAM)
Bloodstorm:
2 * MS62256 = 2 * 32k = 64k (main RAM)
6 * V52C8128K = 6 * 128k = 768k (video RAM)
3 * MB84256 = 3 * 32k = 96k (palette RAM)
Driver's Edge:
4 * CXK58258 = 4 * 32k = 128k (main RAM)
4 * CY7C199 = 4 * 32k = 128k (main RAM)
8 * V52C8128K = 8 * 128k = 1024k (video RAM)
3 * CXK58257AM = 3 * 32k = 96k (palette RAM)
8 * CY7C141 = 8 * 1k = 8k (dual ported shared RAM btw 68k and TMS)
8 * CXK581000AM= 8 * 128k = 1024k (TMS1 RAM)
4 * CY7C185 = 4 * 8k = 32k (TMS1 RAM)
8 * CY7C199 = 8 * 32k = 256k (TMS2 RAM)
****************************************************************************
Golden Tee 3D / World Class Bowling / Shuffleshot hardware (aka P/N 1083 PCB)
Incredible Technologies, 1996-2002
This covers all the Incredible Technologies games on the single large PCB
PCB Layout
----------
P/N 1083 REV 2
|----------------------------------------------------------------------|
|SROM2 SROM1 SROM0 U88 LH5164 XC7336(2) GRM2_0|
| HM538123 8MHz GRM1_0 |
|SROM4 SROM3 HM538123 GRM0_0 |
| 68B09 CY7C199 HM538123 |------| GRM2_1|
| PAL1 PAL2 HM538123 | IT42 | GRM1_1 |
| CY7C199 HM538123 | | GRM0_1 |
| 16MHz HM538123 |------| GRM2_3|
| ES5506 CY7C199 GRM1_2 |
| PROM1 PROM0 CY7C185 GRM0_2 |
| TDA1543 LED CY7C185 68EC020 GRM2_3|
| X9312WS X9312WS CY7C185 25MHz GRM1_3 |
| 3403 TC551001 CY7C185 GRM0_3 |
|TICKETS BATTERY PROM2 PROM3 XC7336(1) PLAYER1|
| LTC691 DSW(4) |
|VOLUME LT723 PLAYER2|
| TDA7240A DSW(4) 4MHz PAL3 |
| PIC16C54 LED |
|------------------------------JAMMA-----------------------------------|
Notes:
68EC020 - clock 25.000MHz
ES5506 - clock 16.000MHz
68B09 - clock 2.000MHz [16/8]
CY7C185 - 8k x8 SRAM
CY7C199 - 32k x8 SRAM
HM528123 - Hitachi HM538123 128k x8 VRAM
TC551001 - Toshiba TC551001 128k x8 SRAM
LH5164 - Sharp LH5164 8k x8 SRAM
XC7336(1) - XILINX XC7336 CPLD labelled 'ITMP3-15'
XC7336(2) - XILINX XC7336 CPLD labelled 'ITVR-1'
IT42 - Custom Incredible Technologies Graphics Generator (QFP208)
Measurements
------------
X1 - 8.00006MHz
X2 - 25.00002MHz
X3 - 4.00000MHz
X5 - 15.99984MHz
VSync - 59.7612Hz
HSync - 15.6570kHz
****************************************************************************
Hot Memory (German V1.2)
Tuning/Strata/Incredible Technologies, 1994
This game is a clone of Pairs and runs on Incredible Technologies 32bit hardware.
PCB Layout
----------
Top (2 separate PCBs plugged into the main board)
---
P/N 1060 REV 0 P/N 1061 REV1
|---------------------------------| |---------------------------------|
|6522 SND.U17 SROM0 | | GROM15 GROM10 |
| 6809 6264 ENSONIC | | |
| | | GROM16 GROM11 |
| LED1 | | |
| PAL1 | | *GROM17 *GROM12 |
| | | |
| *SROM2 *SROM1 | | *GROM18 *GROM13 |
| ES5506 16MHz | | |
| MM5437 | | |
| | | |
| PAL2 | | GROM5 GROM0 |
| | | |
| VOL | | GROM6 GROM1 |
| TDA1543 | | |
| | | *GROM7 *GROM2 |
| 555 3403 3403 | | |
| | | *GROM8 *GROM3 |
| | | |
| JP3 | | *GROM9 *GROM4 |
|---------------------------------| |---------------------------------|
Notes:
* - These locations not populated
ES5506 - Ensoniq ES5506 OTTOR2, clock 16.000MHz
6809 - STMicroelectronics EF68B09, clock 2.000MHz
ENSONIC- DIP42 chip labelled 'ENSONIC (C)1992 2M 1350901601 9320 1.00' at location SROM0
-This is actually a 16MBit DIP42 MaskROM
MM5437 - National Semiconductor MM5437 pseudo-random noise generator chip (DIP8)
LED1 - Sound Status Yellow LED, blinks when active
PAL1 - Labelled 'ITBP-1'
PAL2 - Labelled 'ITSS-1'
JP3 - 4 pin connector for right & left speaker output
Main Board
----------
P/N 1059 REV3
|------------------------------------------------------------------------|
|MC3423 84256 V52C8128K70 |
| |
| |
| 84256 |
| |
| V52C8128K70 |
|A 84256 V52C8128K70 |
|M V52C8128K70 |
|M PAL3 LED2 |
|A PAL4 PAL5 PAL6 PAL7 PAL8|
|J |-----| |
| | | HOTMEM1.U88 |
| | 6 | 62256 |
| | 8 | |----------| |
| | 0 |12MHz 8MHz | | |
| | 0 | HOTMEM0.U83 | IT42 | |
| | 0 | BATTERY 62256 | (QFP208) | |
| | | | | |
|DSW(4) |-----| ADM690 25MHz |----------| |
| J1 J2 |
|------------------------------------------------------------------------|
Notes:
AMMAJ - Note JAMMA connector is backwards!
68000 - clock 12.000MHz
HSync - 15.68kHz
VSync - 60Hz
J1/J2 - 15 Pin Connector For Player 3 & 4 Controls
PAL3 - GAL22V10
PAL4 - Labelled 'ITVS-16A'
PAL5 - Labelled 'ITVS-15'
PAL6 - Labelled 'ITVS-14'
PAL7 - Labelled 'ITVS-13'
PAL8 - Labelled 'ITVS-12'
LED2 - CPU Status Green LED, blinks when active
IT42 - Custom Incredible Technologies Graphics Generator (QFP208)
ADM690- Analog Devices ADM690 4.65V Reset, Battery Switchover, Watchdog Timer, Power Fail Input IC (DIP8)
MC3423- Motorola MC3423 Overvoltage Sensing Circuit (SOIC8)
84256 - Fujitsu MB84256A-10L 32k x8 SRAM (SOP28)
62256 - MOSEL MS62256L-10PC 32k x8 SRAM (DIP28)
V52C8128K70 - Vitelic V52C8128K70 ?? possibly 128k x8 DRAM (SOJ40)
****************************************************************************
Hard Yardage
Strata/Incredible Technologies, 1993
PCB Layout
----------
Top (2 separate PCBs plugged into the main board)
---
P/N 1060 REV 0 P/N 1061 REV 1
|---------------------------------| |---------------------------------|
|6522 SND.U17 SROM0 | | ITFB3 ITFB2 |
| 6809 6264 ENSONIC | | |
| | | ITFB7 ITFB6 |
| LED1 | | |
| PAL1 | | ITFB11 ITFB10 |
| | | |
| *SROM2 SROM1 | | *GROM18 *GROM13 |
| ES5506 16MHz | | |
| MM5437 | | *GROM19 *GROM14 |
| | | |
| PAL2 | | ITFB1 ITFB0 |
| | | |
| VOL | | ITFB5 ITFB4 |
| TDA1543 | | |
| | | ITFB9 ITFB8 |
| 555 3403 3403 | | |
| | | *GROM8 *GROM3 |
| | | |
| JP3 | | *GROM9 *GROM4 |
|---------------------------------| |---------------------------------|
Notes:
Same main board (P/N 1059 REV3) & sound PCB(P/N 1060 REV 0) as shown above.
* - These locations not populated
****************************************************************************
World Class Bowling
Incredible Technologies, 1995
PCB Layout
----------
Top (2 separate PCBs plugged into the main board)
---
P/N 1060 REV 0 P/N 1079 REV 1
|---------------------------------| |---------------------------------|
|6522 SND.U17 SROM0 | | |
| 6809 6264 ENSONIC | | GRM0_3 GRM0_2 |
| | | |
| LED1 | | GRM1_3 GRM1_2 |
| PAL1 | | |
| | | *GRM2_3 *GRM2_2 |
| *SROM2 SROM1 | | |
| ES5506 16MHz | | |
| MM5437 | | |
| | | GRM0_1 GRM0_0 |
| PAL2 | | |
| | | GRM1_1 GRM1_0 |
| VOL | | |
| TDA1543 | | *GRM2_1 *GRM2_0 |
| | | |
| 555 3403 3403 | | |
| | | ITBWL-1 JP7|
| | | 4MHz |
| JP3 | | LED JP8|
|---------------------------------| |---------------------------------|
Notes:
Same main board (P/N 1059 REV3) & sound PCB(P/N 1060 REV 0) as shown above.
* - These locations not populated
ENSONIC - DIP42 chip labelled 'ENSONIC (C)1993 2MX16U 1350901801 9312 1.00' at location SROM0
- This is actually a 16MBit DIP42 MaskROM
ITBWL-1 PIC 16C54 used for protection
JP7 6 Pin trackball connector (Player 1)
JP8 6 Pin trackball connector (Player 2)
****************************************************************************
Time Killers
Strata/Incredible Technologies, 1992
Known to use at least 3 different ROM boards:
PCB Layout
----------
P/N 1049 REV 1 P/N 1057 REV 0 P/N 1051 REV 0
|---------------------------------| |---------------------------------| |---------------------------------|
| GROM04 GROM09 | | GROM01 GROM02 | | |
| | | | | |
| GROM03 GROM08 | | Time Killers-3* Time Killers-3* | | |
| | | | | |
| GROM02 GROM07 | | Time Killers-2* Time Killers-2* | | |
| | | | | |
| GROM01 GROM06 | | Time Killers-1* Time Killers-1* | | |
| | | | | R R G G |
| GROM00 GROM05 | | Time Killers-0* Time Killers-0* | | O O R R |
| | | | | M M O O |
| GROM14 GROM19 | | GROM03 GROM04 | | 1 2 M M |
| | | | | * * 1 2 |
| GROM13 GROM18 | | Time Killers-3* Time Killers-3* | | |
| | | | | R R G G |
| GROM12 GROM17 | | Time Killers-2* Time Killers-2* | | O O R R |
| | | | | M M O O |
| GROM11 GROM16 | | Time Killers-1* Time Killers-1* | | 3 4 M M |
| | | | | * * 3 4 |
| GROM10 GROM15 | | Time Killers-0* Time Killers-0* | | |
|---------------------------------| |---------------------------------| |---------------------------------|
Notes:
P/N 1050 REV1 main board & P/N 1052 REV 2 sound PCB
* denotes 42 pin mask ROM
****************************************************************************/
#include "emu.h"
#include "itech32.h"
#include "cpu/m6800/m6801.h"
#include "cpu/m68000/m68000.h"
#include "cpu/m68000/m68020.h"
#include "cpu/m6809/m6809.h"
#include "cpu/tms32031/tms32031.h"
#include "machine/input_merger.h"
#include "machine/nvram.h"
#include "machine/watchdog.h"
#include "speaker.h"
#define LOG_SCREEN (1U << 1)
#define LOG_PIA (1U << 2)
#define LOG_RAM (1U << 3)
#define LOG_ALL (LOG_SCREEN | LOG_PIA | LOG_RAM)
#define VERBOSE (0)
#include "logmacro.h"
#define LOGSCREEN(...) LOGMASKED(LOG_SCREEN, __VA_ARGS__)
#define LOGPIA(...) LOGMASKED(LOG_PIA, __VA_ARGS__)
#define LOGRAM(...) LOGMASKED(LOG_RAM, __VA_ARGS__)
#define START_TMS_SPINNING(n) do { space.device().execute().spin_until_trigger(7351 + n); m_tms_spinning[n] = 1; } while (0)
#define STOP_TMS_SPINNING(machine, n) do { (machine).scheduler().trigger(7351 + n); m_tms_spinning[n] = 0; } while (0)
static constexpr XTAL CPU020_CLOCK = XTAL(25'000'000); // clock for 68EC020-based systems
/*************************************
*
* Interrupt handling
*
*************************************/
void shoottv_state::update_interrupts(int vint, int xint, int qint)
{
// VINT is ignored on shoottv hardware.
itech32_state::update_interrupts(-1, xint, qint);
}
void itech32_state::update_interrupts(int vint, int xint, int qint)
{
// update the states
if (vint != -1) m_vint_state = vint;
if (xint != -1) m_xint_state = xint;
if (qint != -1) m_qint_state = qint;
m_maincpu->set_input_line(1 + m_irq_base, m_vint_state ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(2 + m_irq_base, m_xint_state ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(3 + m_irq_base, m_qint_state ? ASSERT_LINE : CLEAR_LINE);
}
void itech32_state::generate_int1(int state)
{
if (state)
{
// signal the NMI
update_interrupts(1, -1, -1);
LOGSCREEN("------------ VBLANK (%d) --------------\n", m_screen->vpos());
}
}
void itech32_state::int1_ack_w(u16 data)
{
update_interrupts(0, -1, -1);
}
/*************************************
*
* Machine initialization
*
*************************************/
void itech32_state::machine_start()
{
m_soundbank->configure_entries(0, 256, memregion("soundcpu")->base() + 0x10000, 0x4000);
m_irq_base = 0;
save_item(NAME(m_vint_state));
save_item(NAME(m_xint_state));
save_item(NAME(m_qint_state));
save_item(NAME(m_irq_base));
save_item(NAME(m_sound_return));
save_item(NAME(m_special_result));
save_item(NAME(m_effx));
save_item(NAME(m_effy));
save_item(NAME(m_lastresult));
save_item(NAME(m_lasttime));
}
void itech32_state::machine_reset()
{
m_vint_state = m_xint_state = m_qint_state = 0;
m_sound_return = 0;
}
void drivedge_state::machine_start()
{
itech32_state::machine_start();
m_leds.resolve();
save_item(NAME(m_tms_spinning));
#if LOG_DRIVEDGE_UNINIT_RAM
save_item(NAME(m_written));
#endif
}
void drivedge_state::machine_reset()
{
itech32_state::machine_reset();
m_dsp[0]->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
m_dsp[1]->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
STOP_TMS_SPINNING(machine(), 0);
STOP_TMS_SPINNING(machine(), 1);
m_irq_base = 2;
}
/*************************************
*
* Color latches
*
*************************************/
template<unsigned Layer>
void itech32_state::color_w(u8 data)
{
m_color_latch[Layer] = (data & 0x7f) << 8;
}
/*************************************
*
* Input handlers
*
*************************************/
int itech32_state::special_port_r()
{
if ((!machine().side_effects_disabled()) && m_soundlatch->pending_r())
m_special_result ^= 1;
return m_special_result;
}
template<unsigned Which>
u8 itech32_state::trackball_r()
{
const u8 lower = m_trackball_x[Which]->read();
const u8 upper = m_trackball_y[Which]->read();
return (lower & 15) | ((upper & 15) << 4);
}
u16 itech32_state::trackball_8bit_r()
{
const u8 lower = m_trackball_x[0]->read();
const u8 upper = m_trackball_y[0]->read();
return (lower & 255) | (u16(upper & 255) << 8);
}
template<unsigned Which>
u32 itech32_state::trackball32_4bit_r()
{
attotime curtime = machine().time();
if ((curtime - m_lasttime[Which]) > m_screen->scan_period())
{
const s32 curx = m_trackball_x[Which]->read();
const s32 cury = m_trackball_y[Which]->read();
int dx = curx - m_effx[Which];
if (dx < -0x80) dx += 0x100;
else if (dx > 0x80) dx -= 0x100;
if (dx > 7) dx = 7;
else if (dx < -7) dx = -7;
m_effx[Which] = (m_effx[Which] + dx) & 0xff;
const u8 lower = m_effx[Which] & 15;
int dy = cury - m_effy[Which];
if (dy < -0x80) dy += 0x100;
else if (dy > 0x80) dy -= 0x100;
if (dy > 7) dy = 7;
else if (dy < -7) dy = -7;
m_effy[Which] = (m_effy[Which] + dy) & 0xff;
const u8 upper = m_effy[Which] & 15;
m_lastresult[Which] = lower | (upper << 4);
}
m_lasttime[Which] = curtime;
return m_lastresult[Which] | (u32(m_lastresult[Which]) << 16);
}
u32 itech32_state::trackball32_4bit_combined_r()
{
return trackball32_4bit_r<0>() |
(trackball32_4bit_r<1>() << 8);
}
u16 drivedge_state::steering_r()
{
s32 val = m_steer->read() * 2 - 0x100;
if (val < 0) val = 0x100 | (-val);
return val;
}
u16 drivedge_state::gas_r()
{
return m_gas->read();
}
/*************************************
*
* Protection is handled through a PIC 16C54 MCU
*
*************************************/
u16 itech32_state::wcbowl_prot_result_r()
{
return m_nvram16[0x111d/2];
}
u8 itech32_state::itech020_prot_result_r()
{
u32 result = m_main_ram32[m_itech020_prot_address >> 2];
result >>= (~m_itech020_prot_address & 3) * 8;
return result & 0xff;
}
u32 itech32_state::gt2kp_prot_result_r()
{
return 0x00010000; // 32 bit value at 680000 to 680003 will return the needed value of 0x01
}
u32 itech32_state::gtclass_prot_result_r()
{
return 0x00008000; // 32 bit value at 680000 to 680003 will return the needed value of 0x80
}
/*************************************
*
* Sound banking
*
*************************************/
void itech32_state::sound_bank_w(u8 data)
{
m_soundbank->set_entry(data);
}
/*************************************
*
* Sound communication
*
*************************************/
void itech32_state::sound_data_w(u8 data)
{
// seems hacky, but sound CPU should lose fewer bytes this way
if (m_soundlatch2.found() && m_soundlatch->pending_r())
m_soundlatch2->write(data);
else
m_soundlatch->write(data);
}
u8 itech32_state::sound_return_r()
{
return m_sound_return;
}
void itech32_state::sound_return_w(u8 data)
{
m_sound_return = data;
}
u8 itech32_state::sound_data_buffer_r()
{
return m_soundlatch->pending_r() << 7;
}
void itech32_state::sound_control_w(u8 data)
{
}
/*************************************
*
* Sound I/O port handling
*
*************************************/
void drivedge_state::portb_out(u8 data)
{
// LOGPIA("PIA port B write = %02x\n", data);
// bit 0 controls the fan light
// bit 1 controls the tow light
// bit 2 controls the horn light
// bit 4 controls the ticket dispenser
// bit 5 controls the coin counter
// bit 6 controls the diagnostic sound LED
m_leds[1] = BIT(data, 0);
m_leds[2] = BIT(data, 1);
m_leds[3] = BIT(data, 2);
m_ticket->motor_w(BIT(data, 4));
machine().bookkeeping().coin_counter_w(0, BIT(data, 5));
}
void drivedge_state::turbo_light(int state)
{
m_leds[0] = state ? 1 : 0;
}
void itech32_state::pia_portb_out(u8 data)
{
// LOGPIA("PIA port B write = %02x\n", data);
// bit 4 controls the ticket dispenser
// bit 5 controls the coin counter
// bit 6 controls the diagnostic sound LED
m_ticket->motor_w(BIT(data, 4));
machine().bookkeeping().coin_counter_w(0, BIT(data, 5));
}
/*************************************
*
* Additional sound code
*
*************************************/
void itech32_state::firq_clear_w(u8 data)
{
m_soundcpu->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
}
/*************************************
*
* Driver's Edge stuff
*
*************************************/
void drivedge_state::tms_reset_assert_w(u32 data)
{
m_dsp[0]->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
m_dsp[1]->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
}
void drivedge_state::tms_reset_clear_w(u32 data)
{
// kludge to prevent crash on first boot
if ((m_tms1_ram[0] & 0xff000000) == 0)
{
m_dsp[0]->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
STOP_TMS_SPINNING(machine(), 0);
}
if ((m_tms2_ram[0] & 0xff000000) == 0)
{
m_dsp[1]->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
STOP_TMS_SPINNING(machine(), 1);
}
}
void drivedge_state::tms1_68k_ram_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_tms1_ram[offset]);
if (offset == 0) COMBINE_DATA(m_tms1_boot);
if (offset == 0x382 && m_tms_spinning[0]) STOP_TMS_SPINNING(machine(), 0);
if (!m_tms_spinning[0])
machine().scheduler().add_quantum(attotime::from_hz(CPU020_CLOCK/256), attotime::from_usec(20));
}
void drivedge_state::tms2_68k_ram_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_tms2_ram[offset]);
if (offset == 0x382 && m_tms_spinning[1]) STOP_TMS_SPINNING(machine(), 1);
if (!m_tms_spinning[1])
machine().scheduler().add_quantum(attotime::from_hz(CPU020_CLOCK/256), attotime::from_usec(20));
}
void drivedge_state::tms1_trigger_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_tms1_ram[offset]);
machine().scheduler().add_quantum(attotime::from_hz(CPU020_CLOCK/256), attotime::from_usec(20));
}
void drivedge_state::tms2_trigger_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(&m_tms2_ram[offset]);
machine().scheduler().add_quantum(attotime::from_hz(CPU020_CLOCK/256), attotime::from_usec(20));
}
u32 drivedge_state::tms1_speedup_r(address_space &space)
{
if (m_tms1_ram[0x382] == 0 && m_dsp[0]->pc() == 0xee) START_TMS_SPINNING(0);
return m_tms1_ram[0x382];
}
u32 drivedge_state::tms2_speedup_r(address_space &space)
{
if (m_tms2_ram[0x382] == 0 && m_dsp[1]->pc() == 0x809808) START_TMS_SPINNING(1);
return m_tms2_ram[0x382];
}
/*************************************
*
* NVRAM read/write
*
*************************************/
void itech32_state::nvram_init(nvram_device &nvram, void *base, size_t length)
{
// if nvram is the main RAM, don't overwrite exception vectors
const int start = (!m_main_ram32) && (base == m_nvram32 || base == m_nvram16) ? 0x80 : 0x00;
for (int i = start; i < length; i++)
((u8 *)base)[i] = machine().rand();
}
void drivedge_state::nvram_init(nvram_device &nvram, void *base, size_t length)
{
itech32_state::nvram_init(nvram, base, length);
// due to accessing uninitialized RAM, we need this hack
m_nvram32[0x2ce4/4] = 0x0000001e;
}
/*************************************
*
* Main CPU memory handlers
*
*************************************/
//------ Time Killers memory layout ------
void itech32_state::timekill_map(address_map &map)
{
map(0x000000, 0x003fff).ram().share(m_nvram16);
map(0x040000, 0x040001).portr("P1");
map(0x048000, 0x048001).portr("P2");
map(0x050000, 0x050001).portr("SYSTEM");
map(0x050001, 0x050001).w(FUNC(itech32_state::timekill_intensity_w));
map(0x058000, 0x058001).portr("DIPS").w("watchdog", FUNC(watchdog_timer_device::reset16_w));
map(0x060000, 0x060003).w(FUNC(itech32_state::timekill_colora_w));
map(0x068000, 0x068003).w(FUNC(itech32_state::timekill_colorbc_w));
map(0x070000, 0x070001).nopw(); // noisy
map(0x078001, 0x078001).w(FUNC(itech32_state::sound_data_w));
map(0x080000, 0x08007f).rw(FUNC(itech32_state::video_r), FUNC(itech32_state::video_w));
map(0x0a0000, 0x0a0001).w(FUNC(itech32_state::int1_ack_w));
map(0x0c0000, 0x0c7fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
map(0x100000, 0x17ffff).rom().region("maindata", 0);
}
//------ BloodStorm and later games memory layout ------
void itech32_state::bloodstm_map(address_map &map)
{
map(0x000000, 0x00ffff).ram().share(m_nvram16);
map(0x080000, 0x080001).portr("P1").w(FUNC(itech32_state::int1_ack_w));
map(0x100000, 0x100001).portr("P2");
map(0x180000, 0x180001).portr("P3");
map(0x200000, 0x200001).portr("P4").w("watchdog", FUNC(watchdog_timer_device::reset16_w));
map(0x280000, 0x280001).portr("DIPS");
map(0x300001, 0x300001).w(FUNC(itech32_state::color_w<0>));
map(0x380001, 0x380001).w(FUNC(itech32_state::color_w<1>));
map(0x400000, 0x400001).w("watchdog", FUNC(watchdog_timer_device::reset16_w));
map(0x480001, 0x480001).w(FUNC(itech32_state::sound_data_w));
map(0x500000, 0x5000ff).rw(FUNC(itech32_state::bloodstm_video_r), FUNC(itech32_state::bloodstm_video_w));
map(0x580000, 0x59ffff).ram().w(FUNC(itech32_state::bloodstm_paletteram_w)).share("palette");
map(0x700001, 0x700001).w(FUNC(itech32_state::bloodstm_plane_w));
map(0x780000, 0x780001).portr("EXTRA");
map(0x800000, 0x87ffff).mirror(0x780000).rom().region("maindata", 0);
}
//------ Driver's Edge memory layouts ------
#if LOG_DRIVEDGE_UNINIT_RAM
u32 drivedge_state::test1_r(offs_t offset, u32 mem_mask)
{
if (!machine().side_effects_disabled())
{
if (ACCESSING_BITS_24_31 && !m_written[0x100 + offset*4+0]) LOGRAM("%06X:read from uninitialized memory %04X\n", m_maincpu->pc(), 0x100 + offset*4+0);
if (ACCESSING_BITS_16_23 && !m_written[0x100 + offset*4+1]) LOGRAM("%06X:read from uninitialized memory %04X\n", m_maincpu->pc(), 0x100 + offset*4+1);
if (ACCESSING_BITS_8_15 && !m_written[0x100 + offset*4+2]) LOGRAM("%06X:read from uninitialized memory %04X\n", m_maincpu->pc(), 0x100 + offset*4+2);
if (ACCESSING_BITS_0_7 && !m_written[0x100 + offset*4+3]) LOGRAM("%06X:read from uninitialized memory %04X\n", m_maincpu->pc(), 0x100 + offset*4+3);
}
return ((u32 *)m_nvram)[0x100/4 + offset];
}
void drivedge_state::test1_w(offs_t offset, u32 data, u32 mem_mask)
{
if (ACCESSING_BITS_24_31) m_written[0x100 + offset*4+0] = 1;
if (ACCESSING_BITS_16_23) m_written[0x100 + offset*4+1] = 1;
if (ACCESSING_BITS_8_15) m_written[0x100 + offset*4+2] = 1;
if (ACCESSING_BITS_0_7) m_written[0x100 + offset*4+3] = 1;
COMBINE_DATA(&((u32 *)m_nvram)[0x100/4 + offset]);
}
u32 drivedge_state::test2_r(offs_t offset, u32 mem_mask)
{
if (!machine().side_effects_disabled())
{
if (ACCESSING_BITS_24_31 && !m_written[0xc00 + offset*4+0]) LOGRAM("%06X:read from uninitialized memory %04X\n", m_maincpu->pc(), 0xc00 + offset*4+0);
if (ACCESSING_BITS_16_23 && !m_written[0xc00 + offset*4+1]) LOGRAM("%06X:read from uninitialized memory %04X\n", m_maincpu->pc(), 0xc00 + offset*4+1);
if (ACCESSING_BITS_8_15 && !m_written[0xc00 + offset*4+2]) LOGRAM("%06X:read from uninitialized memory %04X\n", m_maincpu->pc(), 0xc00 + offset*4+2);
if (ACCESSING_BITS_0_7 && !m_written[0xc00 + offset*4+3]) LOGRAM("%06X:read from uninitialized memory %04X\n", m_maincpu->pc(), 0xc00 + offset*4+3);
}
return ((u32 *)m_nvram)[0xc00/4 + offset];
}
void drivedge_state::test2_w(offs_t offset, u32 data, u32 mem_mask)
{
if (ACCESSING_BITS_24_31) m_written[0xc00 + offset*4+0] = 1;
if (ACCESSING_BITS_16_23) m_written[0xc00 + offset*4+1] = 1;
if (ACCESSING_BITS_8_15) m_written[0xc00 + offset*4+2] = 1;
if (ACCESSING_BITS_0_7) m_written[0xc00 + offset*4+3] = 1;
COMBINE_DATA(&((u32 *)m_nvram)[0xc00/4 + offset]);
}
#endif
void drivedge_state::main_map(address_map &map)
{
map(0x000000, 0x03ffff).mirror(0x40000).ram().share(m_nvram32);
#if LOG_DRIVEDGE_UNINIT_RAM
map(0x000100, 0x0003ff).mirror(0x40000).rw(FUNC(drivedge_state::test1_r), FUNC(drivedge_state::test1_w));
map(0x000c00, 0x007fff).mirror(0x40000).rw(FUNC(drivedge_state::test2_r), FUNC(drivedge_state::test2_w));
#endif
map(0x080000, 0x080003).portr("80000");
map(0x082000, 0x082003).portr("82000");
map(0x084001, 0x084001).rw(FUNC(drivedge_state::sound_return_r), FUNC(drivedge_state::sound_data_w));
// map(0x086000, 0x08623f).ram(); -- networking -- first 0x40 bytes = our data, next 0x40*8 bytes = their data, r/w on IRQ2
map(0x088000, 0x088001).r(FUNC(drivedge_state::steering_r));
map(0x08a000, 0x08a001).r(FUNC(drivedge_state::gas_r));
map(0x08a000, 0x08a003).nopw();
map(0x08c000, 0x08c003).portr("8c000");
map(0x08e000, 0x08e003).portr("8e000").nopw();
map(0x100000, 0x10000f).w(FUNC(drivedge_state::zbuf_control_w)).share(m_zbuf_control);
map(0x180001, 0x180001).w(FUNC(drivedge_state::color_w<0>));
map(0x1a0000, 0x1bffff).ram().w(m_palette, FUNC(palette_device::write32)).share("palette");
map(0x1c0000, 0x1c0003).nopw();
map(0x1e0000, 0x1e0113).rw(FUNC(drivedge_state::bloodstm_video_r), FUNC(drivedge_state::bloodstm_video_w));
map(0x1e4000, 0x1e4003).w(FUNC(drivedge_state::tms_reset_assert_w));
map(0x1ec000, 0x1ec003).w(FUNC(drivedge_state::tms_reset_clear_w));
map(0x200000, 0x200003).portr("200000");
map(0x280000, 0x280fff).ram().lr32(NAME([this](offs_t offset) { return m_tms1_ram[offset]; })).w(FUNC(drivedge_state::tms1_68k_ram_w));
map(0x300000, 0x300fff).ram().lr32(NAME([this](offs_t offset) { return m_tms2_ram[offset]; })).w(FUNC(drivedge_state::tms2_68k_ram_w));
map(0x380000, 0x380003).nopw(); // .w("watchdog", FUNC(watchdog_timer_device::reset16_w));
map(0x600000, 0x607fff).rom().region("maindata", 0);
}
void drivedge_state::tms1_map(address_map &map)
{
map(0x000000, 0x001fff).ram().share(m_tms1_boot);
map(0x008000, 0x0083ff).mirror(0x400).ram().w(FUNC(drivedge_state::tms1_trigger_w)).share(m_tms1_ram);
map(0x080000, 0x0bffff).ram();
}
void drivedge_state::tms2_map(address_map &map)
{
map(0x000000, 0x0003ff).mirror(0x8400).ram().w(FUNC(drivedge_state::tms2_trigger_w)).share(m_tms2_ram);
map(0x080000, 0x08ffff).ram();