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itech8.cpp
2805 lines (2226 loc) · 118 KB
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itech8.cpp
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// license:BSD-3-Clause
// copyright-holders:Aaron Giles
/***************************************************************************
Incredible Technologies/Strata system
(8-bit blitter variant)
driver by Aaron Giles
Games supported:
* Strata Bowling [3 sets]
* Super Strike Bowling
* Wheel of Fortune [2 sets]
* Grudge Match
* Golden Tee Golf [4 sets]
* Golden Tee Golf II [3 sets]
* Golden Par Golf [2 sets]
* Slick Shot [3 sets]
* Dyno-Bop
* Arlington Horse Racing [2 sets]
* Neck & Neck
* Peggle [2 sets]
* Poker Dice
* Hot Shots Tennis [2 sets]
* Rim Rockin' Basketball [5 sets]
* Ninja Clowns
Known issues:
* None
****************************************************************************
Memory map
****************************************************************************
========================================================================
CPU #1 (6809 games)
========================================================================
Note that many games have the regions 0000-0FFF and 1000-1FFF swapped.
Also, Golden Tee Golf II (V2.2) has most of the addresses in the
0000-0FFF range swizzled randomly.
========================================================================
0100 W xxxxxxxx Unknown
0120 W xxxxxxxx Sound data
0140 R xxxxxxxx Input port
0140 W xxxxxxxx GROM blitter bank select
0160 R xxxxxxxx Input port
0160 W xx------ Display page select
W x------- (upper page select)
W -x------ (unknown)
0180 R xxxxxxxx Input port/DIP switches
0180 W xxxxxxxx Video RAM upper data latch
01A0 W -------- NMI acknowledge (on some boards)
01C0-01C1 R/W xxxxxxxx Blitter chip address high
01C2-01C3 R/W xxxxxxxx Blitter chip address low
01C4-01C5 R/W ---xxxxx Blitter chip flags
R/W ---x---- (render transparent)
R/W ----x--- (expand RLE compressed data)
R/W -----x-- (flip vertically)
R/W ------x- (flip horizontally)
R/W -------x (shift data left 4 bits)
01C6-01C7 R x------- Blitter chip status (1=busy)
01C6-01C7 W -------- Blitter chip trigger
01C8-01C9 R/W xxxxxxxx Blitter chip source width
01CA-01CB R/W xxxxxxxx Blitter chip source height
01CC-01CD R/W xxxxxxxx Blitter chip source data mask
01CE-01CF R/W xxxxxxxx Blitter chip output port
W --x----- (main program ROM bank select)
01D0-01D1 R/W xxxxxxxx Blitter chip X starting coordinate
01D2-01D3 R/W xxxxxxxx Blitter chip maximum scanline count
01D4-01D5 R/W xxxxxxxx Blitter chip X ending coordinate
01D6-01D7 R/W xxxxxxxx Blitter chip initial scanline skip
01D8-01DF R xxxxxxxx Blitter chip input ports
01E0 W xxxxxxxx Palette address latch
01E2-01E3 W --xxxxxx Palette data latches
1000-11FF R/W xxxxxxxx TMS34061 register access
1200-13FF R/W xxxxxxxx TMS34061 XY addressing access
1400-15FF R/W xxxxxxxx TMS34061 register access
1600-17FF R/W xxxxxxxx TMS34061 direct access
1800-19FF R/W xxxxxxxx TMS34061 shift register read
1A00-1BFF R/W xxxxxxxx TMS34061 shift register write
2000-3FFF R/W xxxxxxxx RAM (battery-backed)
4000-7FFF R xxxxxxxx Banked program ROM
8000-FFFF R xxxxxxxx Fixed program ROM
========================================================================
Interrupts:
NMI generated by VBLANK
IRQ generated by TMS34061 scanline interrupt
FIRQ generated by blitter when finished
========================================================================
========================================================================
CPU #1 (68000 games)
========================================================================
000000-003FFF R/W xxxxxxxx xxxxxxxx RAM (battery-backed)
004000-03FFFF R xxxxxxxx xxxxxxxx Main program ROM
100080 W xxxxxxxx -------- Sound data
100100 R xxxxxxxx -------- Input port
100100 W xxxxxxxx -------- GROM blitter bank select
100180 R xxxxxxxx -------- Input port
100100 W xx------ -------- Display page select
W x------- -------- (upper page select)
W -x------ -------- (unknown)
100240 W xxxxxxxx -------- Video RAM upper data latch
100280 R xxxxxxxx -------- Input port/DIP switches
100280 W -------- -------- Unknown
100300-10031F R/W xxxxxxxx xxxxxxxx Blitter chip (as above)
100380 W xxxxxxxx -------- Palette address latch
1003a0 W --xxxxxx -------- Palette data latches
110000-1101FF R/W xxxxxxxx xxxxxxxx TMS34061 register access
110200-1103FF R/W xxxxxxxx xxxxxxxx TMS34061 XY addressing access
110400-1105FF R/W xxxxxxxx xxxxxxxx TMS34061 register access
110600-1107FF R/W xxxxxxxx xxxxxxxx TMS34061 direct access
110800-1109FF R/W xxxxxxxx xxxxxxxx TMS34061 shift register read
110A00-110BFF R/W xxxxxxxx xxxxxxxx TMS34061 shift register write
========================================================================
Interrupts:
INT 3 generated by VBLANK
INT 2 generated by blitter when finished
INT 1 generated by ???
========================================================================
========================================================================
CPU #2
========================================================================
0000 W xxxxxxxx Unknown
1000 R xxxxxxxx Sound command input
2000-2003 R/W xxxxxxxx Yamaha chip I/O
3000-37FF R/W xxxxxxxx RAM
4000 R/W xxxxxxxx OKI 6295 I/O
5000-5003 R/W xxxxxxxx 6521 PIA chip (on early YM3812 boards)
5000-500F R/W xxxxxxxx 6522 VIA chip (on later YM3812 boards)
8000-FFFF R xxxxxxxx Program ROM
========================================================================
Interrupts:
NMI not connected
IRQ generated by write to sound command input
FIRQ generated by Yamaha chip, or by 6522 VIA (if present)
========================================================================
****************************************************************************
PCB layouts
****************************************************************************
Summary:
There are 8 known variants of PCBs for these games. All the PCBs
have the following features in common:
68B09 @ 2 MHz for the main CPU
8k RAM for the main CPU
68B09 @ 2 MHz for the sound CPU
2k RAM for the sound CPU
YM2203C, YM2608B or YM3812 for music
OKI M6295 for speech (except for YM2608B-based system)
TMS34061 for the video controller
ITV4400 custom blitter for rendering
6-bit RAMDAC for palette, or 2xTMS34070NL (Grudge Match only)
From 2-8 64k x 4-bit VRAM chips for frame buffers
An overview of each style PCB is given below:
Wheel Watcher (Wheel of Fortune)-style
* Single board
* YM2203C for music
* 2 VRAM chips for a single 8-bit 256x256 video page
Grudge Match-style
* Single board
* YM2608B for music
* 4 VRAM chips for two 4-bit 512x256 layers
Strata Bowling-style
* Single board
* YM2203C for music
* 3 VRAM chips for an 8-bit 256x256 video background
plus a 4-bit 256x256 video foreground layer
Slick Shot-style
* Single board
* YM2203C for music
* 4 VRAM chips for two 8-bit 256x256 video pages
* additional Z80 and program ROM for sensor reading
Hot Shots Tennis-style
* Single board
* YM3812 for music
* 8 VRAM chips for two 8-bit 512x256 video pages
Rim Rockin' Basketball-style
* Separate main and sound boards
* HD63C09 @ 3MHz replaces 68B09 for main CPU
* YM3812 for music
* 8 VRAM chips for two 8-bit 512x256 video pages
Ninja Clowns-style
* Separate main and sound boards
* 68000 @ 12MHz replaces 68B09 for main CPU
* YM3812 for music
* 8 VRAM chips for two 8-bit 512x256 video pages
Golden Tee Golf II-style
* Separate main and sound boards
* YM3812 for music
* I haven't see one yet, so I can't provide additional details
****************************************************************************
--------------------------------
Wheel Watcher (Wheel of Fortune)
--------------------------------
+------------------------------------+-+
| Bt476KP35 | |
| 12MHz DIPSW4 | |
|(MT42C4064Z-10) | |
|(MT42C4064Z-10) | |
| MT42C4064Z-10 | |
| MT42C4064Z-10 | |
| | |
| TMS34061 +-
| |
| ITV4400 ITVS |
| YM2203C |
| OKI6295 |
| (GROM4) Battery |
| GROM3 CDM6264LE12 SROM0 |
| GROM2 WOF-PGM HY6116 |
| GROM1 WOFSND 8MHz |
| GROM0 |
| MC68B09 MC68B09 |
+--------------------------------------+
GROM0-3 = AM27C256
WOF-PGM = ???
WOFSND = AM27C256
SROM0 = AM27C010
ITVS = ???
MT42C4064Z = 64k x 4 VRAM (2 populated on Wheel of Fortune)
CDM6464 = 8k x 8 RAM
HY6116 = 2k x 8 RAM
Bt476 = 6-bit DAC
TMS34061 = video controller
ITV4400 = IT custom blitter
-------------
Grudge Match
------------
+------------------------------------+-+
| TMS34070NL | |
| TMS34070NL DIPSW4 | |
| TMS4461-15 8MHz | |
| TMS4461-15 | |
| TMS4461-15 | |
| TMS4461-15 | |
| | |
| TMS34061 +-
| |
| ITV4400 |
| GROM6 SROM0 |
| GROM5 |
| GROM4 |
| GROM3 MK40702B-20 YM2608B |
| GROM2 U5-PGM MK6116 |
| GROM1 U27-SND |
| GROM0 |
| MC68B09 MC68B09 |
+--------------------------------------+
GROM0-6 = AM27C010-25
U5-PGM = D27512-25
U27-SND = 27C256-20
SROM0 = AM27C010-25
ITVS = ???
MT42C4064Z = 64k x 4 VRAM (2 populated on Wheel of Fortune)
MK40702B = zero-power RAM
MK6116 = 2k x 8 RAM
TMS34070NL = 16-color RAMDAC
TMS34061 = video controller
ITV4400 = IT custom blitter
------------------------------
Strata Bowling/Golden Tee Golf
------------------------------
+---------------------------------+-+
| IMSG176 | |
| MT42C4064Z-10 | |
| MT42C4064Z-10 | |
| MT42C4064Z-10 12MHz | |
| | |
| TMS34061 DIPSW4 | |
| | |
| ITV4400 +-
| |
| Battery ITVS |
| (GROM5) |
| (GROM4) |
| (GROM3) P5164 |
| GROM2 SBPROG MS6516 SROM0 |
| GROM1 SBSNDS |
| GROM0 8MHz |
| MC68B09 MC68B09 |
+-----------------------------------+
GROM0-3 = AM27C010
SBPROG = 27C256
SBSNDS = 27C256
SROM0 = AM27C010
ITVS = ???
MT42C4064Z = 64k x 4 VRAM
P5164 = 8k x 8 RAM
MS6516 = 2k x 8 RAM
IMSG176 = 6-bit DAC
TMS34061 = video controller
ITV4400 = IT custom blitter
------------------------------
Slick Shot/Poker Dice/Dyno Bop
------------------------------
+------------------------------------+-+
| Z80PGM 4Mhz itvs5 | |
| Z80 rev.1 | |
| | |
| MT42C4064Z-10 MS176-50 | |
| MT42C4064Z-10 | |
| MT42C4064Z-10 12MHz | |
| MT42C4064Z-10 DIPSW4 | |
| +-
| TMS34061 |
| |
| ITV4400 ITVS |
| YM2203C |
| OKI6295 |
| (GROM4) Battery |
| (GROM3) P5164S SROM0 |
| (GROM2) POOLPGM P5116 |
| GROM1 POOLSND 8MHz |
| GROM0 |
| MC68B09 MC68B09 |
+--------------------------------------+
(lower half is almost identical to Wheel of Fortune)
(top contains extra Z80 and logic)
(Z80 and ROM not populated on Poker Dice)
GROM0-1 = AM27C010
POOLPGM = ???
POOLSND = AM27C256
SROM0 = 27C512
ITVS = ???
MT42C4064Z = 64k x 4 VRAM
P5164S = 8k x 8 RAM
P5116 = 2k x 8 RAM
MS176 = 6-bit DAC
TMS34061 = video controller
ITV4400 = IT custom blitter
-----------------------------------
Hot Shots Tennis/Peggle/Neck & Neck
-----------------------------------
(Likely Arlington Horse Racing as well)
+------------------------------------------------+-+
| MT42C4064Z-10 8MHz MS176-50 | |
| MT42C4064Z-10 | |
| MT42C4064Z-10 | |
| MT42C4064Z-10 | |
| MT42C4064Z-10 | |
| MT42C4064Z-10 TMS34061 DIPSW4 | |
| MT42C4064Z-10 12MHz +-
| MT42C4064Z-10 |
| ITV4400 |
| (GROM5) YM3812 OKI6295 |
| (GROM4) Battery ITVS-3 MS6516 |
| (GROM3) P5164 PEG-SND SROM0 |
| GROM2 PEGGLE.BIN 6821 |
| GROM1 |
| GROM0 |
| EF68B09 8MHz EF68B09 |
+--------------------------------------------------+
GROM0-5 = AM27C010
POOLPGM = ???
POOLSND = AM27C256
SROM0 = 27C512
ITVS = ???
MT42C4064Z = 64k x 4 VRAM
P5164S = 8k x 8 RAM
P5116 = 2k x 8 RAM
MS176 = 6-bit DAC
TMS34061 = video controller
ITV4400 = IT custom blitter
----------------------
Rim Rockin' Basketball
----------------------
Lower board
+--------------- --------------------------------+
| | |
+---------------+ MT42C4064Z-10 MT42C4064Z-10 |
| MT42C4064Z-10 MT42C4064Z-10 |
| IMSG176 MT42C4064Z-10 MT42C4064Z-10 |
| MT42C4064Z-10 MT42C4064Z-10 |
| DIPSW4 8MHz ITBP-1 |
| |
| MS6264-10 |
| RRB.BIM TM34061 ITV4400 |
| ITVS-2 |
| GROM02 GROM00 |
| Battery |
| HD63C09 12MHz GROM03 GROM01 |
+------------------------------------------------+
GROM0-3 =
RRB.BIM =
ITVS-2 = ???
MT42C4064Z-10 = 64k x 4 VRAM
MS6264 = 8k x 8 RAM
IMSG176 = 6-bit DAC
TMS34061 = video controller
ITV4400 = IT custom blitter
Sound board
+---------------------------------+
| YM3812 OKI6295 SROM0 |
| ITVS-4 MS6516-10 |
| NCSND |
| |
| EF68B09 |
| |
| 6522 |
| P/N 1038 REV2 |
+---------------------------------+
SROM0 = M27C2001
NCSND = AM27C256
MS6516-10 = 2k x 8 RAM
6522 = VIA
------------
Ninja Clowns
------------
Lower board
+-----------------------------------------------------+-+-
| MS6264 PROM1 (PROM3) DIPSW4 | |
| MS6264 PROM0 (PROM2) | |
| | |
| Battery MC68000P12 | |
| | |
| 12MHz ITVS-5 ITMP-1 | |
| | |
| (GROM7) +-
| (GROM6) 8MHz |
| GROM5 MS176-50 |
| GROM4 |
| GROM3 TMS34061 MT42C4064Z-10 MT42C4064Z-10 |
| GROM2 MT42C4064Z-10 MT42C4064Z-10 |
| GROM1 ITV4400 MT42C4064Z-10 MT42C4064Z-10 |
| GROM0 MT42C4064Z-10 MT42C4064Z-10 |
| P/N 1029 REV3A |
+-------------------------------------------------------+
GROM0-5 = M27C2001
PROM0-1 = AM27C010
ITVS-5 = PAL16L8
ITMP-1 = PAL20R4
MT42C4064Z = 64k x 4 VRAM
MS6264 = 8k x 8 RAM
MS176 = 6-bit DAC
TMS34061 = video controller
ITV4400 = IT custom blitter
Sound board - same as Rim Rockin' Basketball
***************************************************************************/
#include "emu.h"
#include "itech8.h"
#include "cpu/m68000/m68000.h"
#include "cpu/m6809/hd6309.h"
#include "cpu/m6809/m6809.h"
#include "cpu/z80/z80.h"
#include "machine/6522via.h"
#include "machine/6821pia.h"
#include "machine/input_merger.h"
#include "sound/okim6295.h"
#include "sound/ymopn.h"
#include "sound/ymopl.h"
#include "speaker.h"
// configurable logging
#define LOG_PROT (1U << 1)
#define LOG_VIDEO (1U << 2)
#define LOG_CONTROL (1U << 3)
//#define VERBOSE (LOG_GENERAL | LOG_PROT | LOG_VIDEO | LOG_CONTROL)
#include "logmacro.h"
#define LOGPROT(...) LOGMASKED(LOG_PROT, __VA_ARGS__)
#define LOGVIDEO(...) LOGMASKED(LOG_VIDEO, __VA_ARGS__)
#define LOGCONTROL(...) LOGMASKED(LOG_CONTROL, __VA_ARGS__)
static constexpr XTAL CLOCK_8MHz = XTAL(8'000'000);
static constexpr XTAL CLOCK_12MHz = XTAL(12'000'000);
/*************************************
*
* Interrupt handling
*
*************************************/
void itech8_state::update_interrupts(int periodic, int tms34061, int blitter)
{
device_type main_cpu_type = m_maincpu->type();
// update the states
if (periodic != -1) m_periodic_int = periodic;
if (tms34061 != -1) m_tms34061_int = tms34061;
if (blitter != -1) m_blitter_int = blitter;
// handle the 6809 case
if (main_cpu_type == MC6809 || main_cpu_type == HD6309)
{
// just modify lines that have changed
if (periodic != -1) m_maincpu->set_input_line(INPUT_LINE_NMI, periodic ? ASSERT_LINE : CLEAR_LINE);
if (tms34061 != -1) m_maincpu->set_input_line(M6809_IRQ_LINE, tms34061 ? ASSERT_LINE : CLEAR_LINE);
if (blitter != -1) m_maincpu->set_input_line(M6809_FIRQ_LINE, blitter ? ASSERT_LINE : CLEAR_LINE);
}
// handle the 68000 case
else
{
m_maincpu->set_input_line(2, m_blitter_int ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(3, m_periodic_int ? ASSERT_LINE : CLEAR_LINE);
}
}
/*************************************
*
* Interrupt generation
*
*************************************/
TIMER_CALLBACK_MEMBER(itech8_state::irq_off)
{
update_interrupts(0, -1, -1);
}
void itech8_state::generate_nmi(int state)
{
if (state)
{
// signal the NMI
update_interrupts(1, -1, -1);
m_irq_off_timer->adjust(attotime::from_usec(1));
LOGVIDEO("------------ VBLANK (%d) --------------\n", m_screen->vpos());
}
}
void itech8_state::ninclown_irq(int state)
{
// definitely doesn't like the generate_nmi code, so we just generate VBlank irq here instead
if (state)
m_maincpu->set_input_line(3, HOLD_LINE);
}
void itech8_state::nmi_ack_w(u8 data)
{
// doesn't seem to hold for every game (e.g., hstennis)
// m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
}
/*************************************
*
* Machine initialization
*
*************************************/
void sstrike_state::machine_start()
{
// we need to update behind the beam as well
m_behind_beam_update_timer = timer_alloc(FUNC(sstrike_state::behind_the_beam_update), this);
m_behind_beam_update_timer->adjust(m_screen->time_until_pos(0), 32);
slikshot_state::machine_start();
}
void itech8_state::machine_start()
{
if (m_mainbank)
{
if (memregion("maincpu")->bytes() > 0x10000)
{
// rimrockn uses different banking address and more banks
m_mainbank->configure_entries(0, 4, memregion("maincpu")->base() + 0x0000, 0x4000);
}
else
{
m_mainbank->configure_entries(0, 2, memregion("maincpu")->base() + 0x0000, 0x4000);
}
}
if (m_fixed)
{
u8* fixedstart = memregion("maincpu")->base() + memregion("maincpu")->bytes() - 0x8000; // last 0x8000 bytes of the ROM
m_fixed->configure_entry(0, fixedstart);
m_fixed->set_entry(0);
}
m_irq_off_timer = timer_alloc(FUNC(itech8_state::irq_off), this);
m_blitter_done_timer = timer_alloc(FUNC(itech8_state::blitter_done), this);
save_item(NAME(m_grom_bank));
save_item(NAME(m_blitter_int));
save_item(NAME(m_tms34061_int));
save_item(NAME(m_periodic_int));
save_item(NAME(m_pia_porta_data));
save_item(NAME(m_pia_portb_data));
}
void grmatch_state::machine_start()
{
itech8_state::machine_start();
save_item(NAME(m_palcontrol));
save_item(NAME(m_xscroll));
m_palette_timer = timer_alloc(FUNC(grmatch_state::palette_update), this);
}
void itech8_state::machine_reset()
{
// make sure bank 0 is selected
if (m_mainbank)
{
m_mainbank->set_entry(0 ^ m_bankxor);
m_maincpu->reset();
}
// set the visible area
if (m_visarea.width() > 1)
{
m_screen->set_visible_area(m_visarea.min_x, m_visarea.max_x, m_visarea.min_y, m_visarea.max_y);
m_visarea.set(0, 0, 0, 0);
}
}
void grmatch_state::machine_reset()
{
itech8_state::machine_reset();
m_palette_timer->adjust(m_screen->time_until_pos(m_screen->vpos()+1));
}
/*************************************
*
* Bank switching
*
*************************************/
TIMER_CALLBACK_MEMBER(sstrike_state::behind_the_beam_update)
{
int scanline = param >> 8;
const int interval = param & 0xff;
// force a partial update to the current scanline
m_screen->update_partial(scanline);
// advance by the interval, and wrap to 0
scanline += interval;
if (scanline >= 256) scanline = 0;
// set a new timer
m_behind_beam_update_timer->adjust(m_screen->time_until_pos(scanline), (scanline << 8) + interval);
}
/*************************************
*
* Bank switching
*
*************************************/
void itech8_state::blitter_bank_w(offs_t offset, u8 data)
{
// bit 0x20 on address 7 controls CPU banking
if (offset / 2 == 7)
m_mainbank->set_entry(BIT(data, 5) ^ m_bankxor);
// the rest is handled by the video hardware
blitter_w(offset, data);
}
void itech8_state::rimrockn_bank_w(u8 data)
{
// banking is controlled here instead of by the blitter output
m_mainbank->set_entry(data & 3);
}
/*************************************
*
* Input handling
*
*************************************/
int itech8_state::special_r()
{
return m_pia_portb_data & 0x01;
}
/*************************************
*
* 6821 PIA handling
*
*************************************/
void itech8_state::pia_porta_out(u8 data)
{
LOGCONTROL("PIA port A write = %02x\n", data);
m_pia_porta_data = data;
}
void itech8_state::pia_portb_out(u8 data)
{
LOGCONTROL("PIA port B write = %02x\n", data);
// bit 0 provides feedback to the main CPU
// bit 4 controls the ticket dispenser
// bit 5 controls the coin counter
// bit 6 controls the diagnostic sound LED
m_pia_portb_data = data;
m_ticket->motor_w(BIT(data, 4));
machine().bookkeeping().coin_counter_w(0, BIT(data, 5));
}
void itech8_state::ym2203_portb_out(u8 data)
{
LOGCONTROL("YM2203 port B write = %02x\n", data);
// bit 0 provides feedback to the main CPU
// bit 5 controls the coin counter
// bit 6 controls the diagnostic sound LED
// bit 7 controls the ticket dispenser
m_pia_portb_data = data;
m_ticket->motor_w(BIT(data, 7));
machine().bookkeeping().coin_counter_w(0, BIT(data, 5));
}
/*************************************
*
* Sound communication
*
*************************************/
void itech8_state::gtg2_sound_data_w(u8 data)
{
// on the later GTG2 board, they swizzle the data lines
data = ((data & 0x80) >> 7) |
((data & 0x5d) << 1) |
((data & 0x20) >> 3) |
((data & 0x02) << 5);
m_soundlatch->write(data);
}
void itech8_state::grom_bank_w(u8 data)
{
m_grom_bank = data;
}
/*************************************
*
* 16-bit-specific handlers
*
*************************************/
u16 itech8_state::rom_constant_r(offs_t offset)
{
// Ninja Clowns reads this area for program ROM checksum
if (!machine().side_effects_disabled())
LOGPROT("Read ROM constant area %04x\n",offset*2+0x40000);
return 0xd840;
}
u8 itech8_state::ninclown_palette_r(offs_t offset)
{
return m_tlc34076->read(offset / 16);
}
void itech8_state::ninclown_palette_w(offs_t offset, u8 data)
{
m_tlc34076->write(offset / 16, data);
}
/*************************************
*
* Main CPU memory handlers
*
*************************************/
//------ common layout with TMS34061 at 0000 ------
void itech8_state::common_lo_map(address_map &map)
{
map(0x0000, 0x0fff).rw(FUNC(itech8_state::tms34061_r), FUNC(itech8_state::tms34061_w));
map(0x1100, 0x1100).nopw();
map(0x1120, 0x1120).w(m_soundlatch, FUNC(generic_latch_8_device::write));
map(0x1140, 0x1140).portr("40").w(FUNC(itech8_state::grom_bank_w));
map(0x1160, 0x1160).portr("60").w(FUNC(itech8_state::page_w));
map(0x1180, 0x1180).portr("80").w(m_tms34061, FUNC(tms34061_device::latch_w));
map(0x11a0, 0x11a0).w(FUNC(itech8_state::nmi_ack_w));
map(0x11c0, 0x11df).rw(FUNC(itech8_state::blitter_r), FUNC(itech8_state::blitter_bank_w));
map(0x11e0, 0x11ff).w(FUNC(itech8_state::palette_w));
map(0x2000, 0x3fff).ram().share("nvram");
map(0x4000, 0x7fff).bankr(m_mainbank);
map(0x8000, 0xffff).bankr(m_fixed); // non-banked area
}
//------ common layout with TMS34061 at 1000 ------
void itech8_state::common_hi_map(address_map &map)
{
map(0x0100, 0x0100).nopw();
map(0x0120, 0x0120).w(m_soundlatch, FUNC(generic_latch_8_device::write));
map(0x0140, 0x0140).portr("40").w(FUNC(itech8_state::grom_bank_w));
map(0x0160, 0x0160).portr("60").w(FUNC(itech8_state::page_w));
map(0x0180, 0x0180).portr("80").w(m_tms34061, FUNC(tms34061_device::latch_w));
map(0x01a0, 0x01a0).w(FUNC(itech8_state::nmi_ack_w));
map(0x01c0, 0x01df).rw(FUNC(itech8_state::blitter_r), FUNC(itech8_state::blitter_bank_w));
map(0x01e0, 0x01ff).w(FUNC(itech8_state::palette_w));
map(0x1000, 0x1fff).rw(FUNC(itech8_state::tms34061_r), FUNC(itech8_state::tms34061_w));
map(0x2000, 0x3fff).ram().share("nvram");
map(0x4000, 0x7fff).bankr(m_mainbank);
map(0x8000, 0xffff).bankr(m_fixed); // non-banked area
}
//------ Grudge Match layout ------
void grmatch_state::grmatch_map(address_map &map)
{
itech8_state::common_hi_map(map);
map(0x0160, 0x0160).w(FUNC(grmatch_state::palette_w));
map(0x0180, 0x0180).w(FUNC(grmatch_state::xscroll_w));
map(0x01e0, 0x01ff).nopw();
}
//------ Slick Shot layout ------
void slikshot_state::mem_hi_map(address_map &map)
{
common_hi_map(map);
map(0x0180, 0x0180).r(FUNC(slikshot_state::z80_r));
map(0x01cf, 0x01cf).rw(FUNC(slikshot_state::z80_control_r), FUNC(slikshot_state::z80_control_w));
}
//------ Super Strike Bowling layout ------
void slikshot_state::mem_lo_map(address_map &map)
{
common_lo_map(map);
map(0x1180, 0x1180).r(FUNC(slikshot_state::z80_r));
map(0x11cf, 0x11cf).rw(FUNC(slikshot_state::z80_control_r), FUNC(slikshot_state::z80_control_w));
}
//------ Rim Rockin' Basketball layout ------
void itech8_state::rimrockn_map(address_map &map)
{
common_hi_map(map);
map(0x0161, 0x0161).portr("161");
map(0x0162, 0x0162).portr("162");
map(0x0163, 0x0163).portr("163");
map(0x0164, 0x0164).portr("164");
map(0x0165, 0x0165).portr("165");
map(0x01a0, 0x01a0).w(FUNC(itech8_state::rimrockn_bank_w));
map(0x01c0, 0x01df).w(FUNC(itech8_state::blitter_w));
}
//------ Golden Tee Golf II 1992 layout ------
void itech8_state::gtg2_map(address_map &map)
{
map(0x0100, 0x0100).portr("40").w(FUNC(itech8_state::nmi_ack_w));
map(0x0120, 0x0120).portr("60").w(FUNC(itech8_state::page_w));
map(0x0140, 0x015f).w(FUNC(itech8_state::palette_w));
map(0x0140, 0x0140).portr("80");
map(0x0160, 0x0160).w(FUNC(itech8_state::grom_bank_w));
map(0x0180, 0x019f).rw(FUNC(itech8_state::blitter_r), FUNC(itech8_state::blitter_bank_w));
map(0x01c0, 0x01c0).w(FUNC(itech8_state::gtg2_sound_data_w));
map(0x01e0, 0x01e0).w(m_tms34061, FUNC(tms34061_device::latch_w));
map(0x1000, 0x1fff).rw(FUNC(itech8_state::tms34061_r), FUNC(itech8_state::tms34061_w));
map(0x2000, 0x3fff).ram().share("nvram");
map(0x4000, 0x7fff).bankr(m_mainbank);
map(0x8000, 0xffff).bankr(m_fixed); // non-banked area
}
//------ Ninja Clowns layout ------
void itech8_state::ninclown_map(address_map &map)
{
map(0x000000, 0x003fff).ram().share("nvram");
map(0x000000, 0x000007).rom();
map(0x004000, 0x03ffff).rom();
map(0x040000, 0x07ffff).r(FUNC(itech8_state::rom_constant_r));
map(0x100080, 0x100080).w(m_soundlatch, FUNC(generic_latch_8_device::write));
map(0x100100, 0x100100).w(FUNC(itech8_state::grom_bank_w));
map(0x100100, 0x100101).portr("40");
map(0x100180, 0x100180).lw8(NAME([this](u8 data){ page_w(~data); }));
map(0x100180, 0x100181).portr("60");
map(0x100240, 0x100240).w(m_tms34061, FUNC(tms34061_device::latch_w));
map(0x100280, 0x100281).portr("80").nopw();
map(0x100300, 0x10031f).rw(FUNC(itech8_state::blitter_r), FUNC(itech8_state::blitter_w));
map(0x100380, 0x1003ff).rw(FUNC(itech8_state::ninclown_palette_r), FUNC(itech8_state::ninclown_palette_w)).umask16(0xff00);
map(0x110000, 0x110fff).rw(FUNC(itech8_state::tms34061_r), FUNC(itech8_state::tms34061_w));
}
/*************************************
*
* Sound CPU memory handlers
*
*************************************/
//------ YM2203-based sound ------
void itech8_state::sound2203_map(address_map &map)
{
map(0x0000, 0x0000).nopw();
map(0x1000, 0x1000).r(m_soundlatch, FUNC(generic_latch_8_device::read));
map(0x2000, 0x2001).mirror(0x0002).rw("ymsnd", FUNC(ym2203_device::read), FUNC(ym2203_device::write));
map(0x3000, 0x37ff).ram();
map(0x4000, 0x4000).rw("oki", FUNC(okim6295_device::read), FUNC(okim6295_device::write));
map(0x8000, 0xffff).rom();
}
//------ YM2608B-based sound ------
void itech8_state::sound2608b_map(address_map &map)
{
map(0x1000, 0x1000).nopw();
map(0x2000, 0x2000).r(m_soundlatch, FUNC(generic_latch_8_device::read));
map(0x4000, 0x4003).rw("ymsnd", FUNC(ym2608_device::read), FUNC(ym2608_device::write));
map(0x6000, 0x67ff).ram();
map(0x8000, 0xffff).rom();
}