/
namconb1.cpp
2056 lines (1681 loc) · 94.2 KB
/
namconb1.cpp
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// license:BSD-3-Clause
// copyright-holders:Phil Stroffolino
/*
Namco System NB-1
Notes:
- tilemap system is identical to Namco System2
ToDo:
- improve interrupts
- gunbulet force feedback
Main CPU : Motorola 68020 32-bit processor @ 25MHz
Secondary CPUs : C329 + 137 (both custom)
Custom Graphics Chips : GFX:123,145,156,C116 - Motion Objects:C355,187,C347
Sound CPU : C75 (Mitsu M37702 with internal ROM)
PCM Sound chip : C352 (custom)
I/O Chip : 160 (custom)
Board composition : Single board
Known games using this hardware:
- Great Sluggers '93
- Great Sluggers '94
- Gun Bullet / Point Blank
- J-League Soccer V-Shoot
- Nebulas Ray
- Super World Stadium '95
- Super World Stadium '96
- Super World Stadium '97
- The Outfoxies
- Mach Breakers
*****************************************************
Gun Bullet (JPN Ver.)
(c)1994 Namco
KeyCus.:C386
Note: CPU - Main PCB (NB-1)
MEM - MEMEXT OBJ8 PCB at J103 on the main PCB
SPR - MEMEXT SPR PCB at location 5B on the main PCB
- Namco main PCB: NB-1 8634961101, (8634963101)
- MEMEXT OBJ8 PCB: 8635902201, (8635902301)
* - Surface mounted ROMs
# - 32 pin DIP Custom IC (16bytes x 16-bit)
Brief hardware overview
-----------------------
Main processor - MC68EC020FG25 25MHz (100 pin PQFP)
- C329 custom (100 pin PQFP)
- 137 custom PLD (28 pin NDIP)
- C366 Key Custom
Sound processor - C75 custom
(PCM) - C352 custom (100 pin PQFP)
(control inputs) - 160 custom (80 pin PQFP)
GFX - 123 custom (80 pin PQFP)
- 145 custom (80 pin PQFP)
- 156 custom (64 pin PQFP)
- C116 custom (80 pin PQFP)
Motion Objects - C355 custom (160 pin PQFP)
- 187 custom (160 pin PQFP)
- C347 custom (80 pin PQFP)
PCB Jumper Settings
-------------------
Location Setting Alt. Setting
----------------------------------------
JP1 1M 4M
JP2 4M 1M
JP5 <1M 1M
JP6 8M >8M
JP7 4M 1M
JP8 4M 1M
JP9 cON cOFF
JP10 24M (MHz) 12M (MHz)
JP11 24M (MHz) 28M (MHz)
JP12 355 F32
*****************************************************
Super World Stadium '95 (JPN Ver.)
(c)1986-1993 1995 Namco
Namco NB-1 system
KeyCus.:C393
*****************************************************
Super World Stadium '96 (JPN Ver.)
(c)1986-1993 1995 1996 Namco
Namco NB-1 system
KeyCus.:C426
*****************************************************
Super World Stadium '97 (JPN Ver.)
(c)1986-1993 1995 1996 1997 Namco
Namco NB-1 system
KeyCus.:C434
*****************************************************
Great Sluggers Featuring 1994 Team Rosters
(c)1993 1994 Namco / 1994 MLBPA
Namco NB-1 system
KeyCus.:C359
*****************************************************
--------------------------
Nebulasray by NAMCO (1994)
--------------------------
Location Device File ID Checksum
-------------------------------------------------
CPU 13B 27C402 NR1-MPRU B0ED [ MAIN PROG ]
CPU 15B 27C240 NR1-MPRL 90C4 [ MAIN PROG ]
SPR 27C1024 NR1-SPR0 99A6 [ SOUND PRG ]
CPU 5M MB834000B NR1-SHA0 DD59 [ SHAPE ]
CPU 8J MB838000B NR1-CHR0 22A4 [ CHARACTER ]
CPU 9J MB838000B NR1-CHR1 19D0 [ CHARACTER ]
CPU 10J MB838000B NR1-CHR2 B524 [ CHARACTER ]
CPU 11J MB838000B NR1-CHR3 0AF4 [ CHARACTER ]
CPU 5J KM2316000 NR1-VOI0 8C41 [ VOICE ]
MEM IC1 MT26C1600 * NR1-OBJ0L FD7C [ MOTION OBJL ]
MEM IC3 MT26C1600 * NR1-OBJ1L 7069 [ MOTION OBJL ]
MEM IC5 MT26C1600 * NR1-OBJ2L 07DC [ MOTION OBJL ]
MEM IC7 MT26C1600 * NR1-OBJ3L A61E [ MOTION OBJL ]
MEM IC2 MT26C1600 * NR1-OBJ0U 44D3 [ MOTION OBJU ]
MEM IC4 MT26C1600 * NR1-OBJ1U F822 [ MOTION OBJU ]
MEM IC6 MT26C1600 * NR1-OBJ2U DD24 [ MOTION OBJU ]
MEM IC8 MT26C1600 * NR1-OBJ3U F750 [ MOTION OBJU ]
CPU 11D Custom # C366.BIN 1C93 [ KEYCUSTUM ]
Note: CPU - Main PCB (NB-1)
MEM - MEMEXT OBJ8 PCB at J103 on the main PCB
SPR - MEMEXT SPR PCB at location 5B on the main PCB
- Namco main PCB: NB-1 8634961101, (8634963101)
- MEMEXT OBJ8 PCB: 8635902201, (8635902301)
* - Surface mounted ROMs
# - 32 pin DIP Custom IC (16bytes x 16-bit)
Brief hardware overview
-----------------------
Main processor - MC68EC020FG25 25MHz (100 pin PQFP)
- C329 custom (100 pin PQFP)
- 137 custom PLD (28 pin NDIP)
- C366 Key Custom
Sound processor - C75 custom
(PCM) - C352 custom (100 pin PQFP)
(control inputs) - 160 custom (80 pin PQFP)
GFX - 123 custom (80 pin PQFP)
- 145 custom (80 pin PQFP)
- 156 custom (64 pin PQFP)
- C116 custom (80 pin PQFP)
Motion Objects - C355 custom (160 pin PQFP)
- 187 custom (160 pin PQFP)
- C347 custom (80 pin PQFP)
PCB Jumper Settings
-------------------
Location Setting Alt. Setting
----------------------------------------
JP1 1M 4M
JP2 4M 1M
JP5 <1M 1M
JP6 8M >8M
JP7 4M 1M
JP8 4M 1M
JP9 cON cOFF
JP10 24M (MHz) 12M (MHz)
JP11 24M (MHz) 28M (MHz)
JP12 355 F32
Namco System NB2
Games running on this hardware:
- The Outfoxies
- Mach Breakers
Changes from Namco System NB1 include:
- different memory map
- more complex sprite and tile banking
- 2 additional ROZ layers
-----------------------------
The Outfoxies by NAMCO (1994)
-----------------------------
Location Device File ID Checksum
----------------------------------------------------
CPU 11C PRGL 27C4002 OU2-MPRL 166F
CPU 11D PRGU 27C4002 OU2-MPRU F4C1
CPU 5B SPR0 27C240 OU1-SPR0 7361
CPU 20A DAT0 27C4002 OU1-DAT0 FCD1
CPU 20B DAT1 27C4002 OU1-DAT1 0973
CPU 18S SHAPE-R MB83800 OU1-SHAR C922
CPU 12S SHAPE-S MB83400 OU1-SHAS 2820
CPU 6N VOICE0 MB831600 OU1-VOI0 4132
ROM 4C OBJ0L 16Meg SMD OU1-OBJ0L 171B
ROM 8C OBJ0U 16Meg SMD OU1-OBJ0U F961
ROM 4B OBJ1L 16Meg SMD OU1-OBJ1L 1579
ROM 8B OBJ1U 16Meg SMD OU1-OBJ1U E8DF
ROM 4A OBJ2L 16Meg SMD OU1-OBJ2L AE7B
ROM 8A OBJ2U 16Meg SMD OU1-OBJ2U 6588
ROM 6C OBJ3L 16Meg SMD OU1-OBJ3L 9ED3
ROM 9C OBJ3U 16Meg SMD OU1-OBJ3U ED3B
ROM 6B OBJ4L 16Meg SMD OU1-OBJ4L 59D4
ROM 9B OBJ4U 16Meg SMD OU1-OBJ4U 56CA
ROM 3D ROT0 16Meg SMD OU1-ROT0 A615
ROM 3C ROT1 16Meg SMD OU1-ROT1 6C0A
ROM 3B ROT2 16Meg SMD OU1-ROT2 313E
ROM 1D SCR0 16Meg SMD OU1-SCR0 751A
CPU 8B DEC75 PAL16L8A NB1-2
CPU 16N MIXER PAL16V8H NB2-1
CPU 11E SIZE PAL16L8A NB2-2
CPU 22C KEYCUS KeyCustom C390
CPU - Namco NB-2 Main PCB 8639960102 (8639970102)
ROM - Namco NB-2 Mask ROM PCB 8639969800 (8639979800)
- Audio out is Stereo
Jumper Settings:
Setting Alternate
JP1 4M 1M
JP2 GND A20
JP3 GND A20
JP6 4M 1M
JP8 GND A20
JP9 CON COFF
JP10 GND A20
Hardware info:
Main CPU: MC68EC020FG25
Custom C383 (100 pin PQFP)
Custom C385 (144 pin PQFP)
Slave CPU: ?Custom C382 (160 pin PQFP)
Custom 160 ( 80 pin PQFP)
Custom C352 (100 pin PQFP)
GFX: Custom 145 ( 80 pin PQFP)
Custom 156 ( 64 pin PQFP)
Custom 123 ( 64 pin PQFP)
3x Custom 384 ( 48 pin PQFP)
Custom C355 (160 pin PQFP)
Custom 187 (120 pin PQFP)
Custom 169 (120 pin PQFP)
*/
#include "emu.h"
#include "namconb1.h"
#include "cpu/m68000/m68020.h"
#include "sound/c352.h"
#include "speaker.h"
#define MASTER_CLOCK XTAL(48'384'000)
#define ENABLE_LOGGING (0)
void namconb1_state::machine_start()
{
save_item(NAME(m_vbl_irq_level));
save_item(NAME(m_pos_irq_level));
save_item(NAME(m_unk_irq_level));
save_item(NAME(m_count));
save_item(NAME(m_port6));
}
/****************************************************************************/
TIMER_DEVICE_CALLBACK_MEMBER(namconb1_state::scantimer)
{
int scanline = param;
// Handle VBLANK
if (scanline == 224)
{
if (m_vbl_irq_level != 0)
m_maincpu->set_input_line(m_vbl_irq_level, ASSERT_LINE);
}
// Handle POSIRQ
u32 posirq_scanline = m_c116->get_reg(5) - 32;
if (scanline == posirq_scanline)
{
m_screen->update_partial(m_update_to_line_before_posirq ? posirq_scanline-1 : posirq_scanline);
if (m_pos_irq_level != 0)
m_maincpu->set_input_line(m_pos_irq_level, ASSERT_LINE);
}
/*
// TODO: Real sources of these
if (scanline == 224)
m_mcu->set_input_line(M37710_LINE_IRQ0, HOLD_LINE);
else if (scanline == 0)
m_mcu->set_input_line(M37710_LINE_IRQ2, HOLD_LINE);
else if (scanline == 128)
m_mcu->set_input_line(M37710_LINE_ADC, HOLD_LINE);
*/
}
TIMER_DEVICE_CALLBACK_MEMBER(namconb1_state::mcu_irq0_cb)
{
m_mcu->set_input_line(M37710_LINE_IRQ0, HOLD_LINE);
}
TIMER_DEVICE_CALLBACK_MEMBER(namconb1_state::mcu_irq2_cb)
{
m_mcu->set_input_line(M37710_LINE_IRQ2, HOLD_LINE);
}
/****************************************************************************/
void namconb1_state::namconb1_cpureg_w(offs_t offset, u8 data)
{
/**
* 400000 0x00
* 400001 POS IRQ enable/level
* 400002 ??? IRQ enable/level
* 400003 0x00
* 400004 VBL IRQ enable/level
* 400005 0x00
* 400006 POS IRQ ack
* 400007 ??? IRQ ack
* 400008 0x00
* 400009 VBL IRQ ack
* 40000a ??? (0x00)
* 40000b ??? (0x03)
* 40000c ??? (0x07)
* 40000d ??? (0x01)
* 40000e ??? (0x10)
* 40000f ??? (0x03)
* 400010 ??? (0x00)
* 400011 ??? (0x07)
* 400012 ??? (0x10)
* 400013 ??? (0x10)
* 400014 ??? (0x00)
* 400015 ??? (0x01)
* 400016 Watchdog
* 400017 ??? (0x00)
* 400018 C75 Control
* 400019 ??? (0x00)
* 40001a ??? (0x00)
* 40001b ??? (0x00)
* 40001c ??? (0x00)
* 40001d ??? (0x00)
* 40001e ??? (0x00)
* 40001f ??? (0x00)
*/
switch (offset)
{
case 0x01:
// Bits 5-4 unknown
m_maincpu->set_input_line(m_pos_irq_level, CLEAR_LINE);
m_pos_irq_level = data & 0x0f;
break;
case 0x02:
m_maincpu->set_input_line(m_unk_irq_level, CLEAR_LINE);
m_unk_irq_level = data & 0x0f;
break;
case 0x04:
m_maincpu->set_input_line(m_vbl_irq_level, CLEAR_LINE);
m_vbl_irq_level = data & 0x0f;
break;
case 0x06:
m_maincpu->set_input_line(m_pos_irq_level, CLEAR_LINE);
break;
case 0x07:
m_maincpu->set_input_line(m_unk_irq_level, CLEAR_LINE);
break;
case 0x09:
m_maincpu->set_input_line(m_vbl_irq_level, CLEAR_LINE);
break;
case 0x16:
break;
case 0x18:
if (data & 1)
{
m_mcu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
m_mcu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
m_mcu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
}
else
m_mcu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
break;
default:
if (ENABLE_LOGGING)
logerror("Unhandled CPU reg write to [0x%.2x] with 0x%.2x (PC=0x%x)\n", offset, data, m_maincpu->pc());
}
}
void namconb1_state::namconb2_cpureg_w(offs_t offset, u8 data)
{
/**
* f00000 VBL IRQ enable/level
* f00001 ??? IRQ enable/level
* f00002 POS IRQ enable/level
* f00003 ??? (0x00)
* f00004 VBL IRQ ack
* f00005 ??? IRQ ack
* f00006 POS IRQ ack
* f00007
* f00008
* f00009 ??? (0x62)
* f0000a ??? (0x0f)
* f0000b ??? (0x41)
* f0000c ??? (0x70)
* f0000d ??? (0x70)
* f0000e ??? (0x23)
* f0000f ??? (0x50)
* f00010 ??? (0x00)
* f00011 ??? (0x64)
* f00012 ??? (0x18)
* f00013 ??? (0xe7)
* f00014 Watchdog
* f00015
* f00016 C75 Control
* f00017
* f00018
* f00019
* f0001a
* f0001b
* f0001c
* f0001d
* f0001e ??? (0x00)
* f0001f ??? (0x01)
*/
switch (offset)
{
case 0x00:
m_maincpu->set_input_line(m_vbl_irq_level, CLEAR_LINE);
m_vbl_irq_level = data & 0x0f;
break;
case 0x01:
m_maincpu->set_input_line(m_unk_irq_level, CLEAR_LINE);
m_unk_irq_level = data & 0x0f;
break;
case 0x02:
m_maincpu->set_input_line(m_pos_irq_level, CLEAR_LINE);
m_pos_irq_level = data & 0x0f;
break;
case 0x04:
m_maincpu->set_input_line(m_vbl_irq_level, CLEAR_LINE);
break;
case 0x05:
m_maincpu->set_input_line(m_unk_irq_level, CLEAR_LINE);
break;
case 0x06:
m_maincpu->set_input_line(m_pos_irq_level, CLEAR_LINE);
break;
case 0x14:
break;
case 0x16:
if (data & 1)
{
m_mcu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
m_mcu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
m_mcu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
}
else
{
m_mcu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
}
break;
default:
if (ENABLE_LOGGING)
logerror("Unhandled CPU reg write to [0x%.2x] with 0x%.2x (PC=0x%x)\n", offset, data, m_maincpu->pc());
}
}
u8 namconb1_state::namconb1_cpureg_r(offs_t offset)
{
// 16: Watchdog
if (ENABLE_LOGGING)
{
if (offset != 0x16)
logerror("Unhandled CPU reg read from [0x%.2x] (PC=0x%x)\n", offset, m_maincpu->pc());
}
return 0xff;
}
u8 namconb1_state::namconb2_cpureg_r(offs_t offset)
{
// 14: Watchdog
if (ENABLE_LOGGING)
{
if (offset != 0x14)
logerror("Unhandled CPU reg read from [0x%.2x] (PC=0x%x)\n", offset, m_maincpu->pc());
}
return 0xff;
}
/****************************************************************************/
u32 namconb1_state::custom_key_r(offs_t offset)
{
u16 old_count = m_count;
do
{ /* pick a random number, but don't pick the same twice in a row */
m_count = machine().rand();
} while (m_count == old_count);
switch (m_gametype)
{
/*
Gunbullet/Point Blank keycus notes (thanks Guru):
These games use the keycus in an unconventional way. Instead of reading it for a PRNG or a
magic value, it writes a scratch value to the keycus once per frame.
On hardware, if there is no keycus or the wrong keycus is present, this write will stall the
68000 (probably nothing completes the bus cycle in that case) and the game will hang instead
of booting.
Patching these writes out causes the game to run fine with no keycus present.
*/
case NAMCONB1_GUNBULET:
return 0;
case NAMCONB1_SWS95:
switch (offset)
{
case 0: return 0x0189;
case 1: return m_count << 16;
}
break;
case NAMCONB1_SWS96:
switch (offset)
{
case 0: return 0x01aa << 16;
case 4: return m_count << 16;
}
break;
case NAMCONB1_SWS97:
switch (offset)
{
case 2: return 0x1b2 << 16;
case 5: return m_count << 16;
}
break;
case NAMCONB1_GSLGR94U:
switch (offset)
{
case 0: return 0x0167;
case 1: return m_count << 16;
}
break;
case NAMCONB1_GSLGR94J:
switch (offset)
{
case 1: return 0;
case 3: return (0x0171 << 16) | m_count;
}
break;
case NAMCONB1_NEBULRAY:
switch (offset)
{
case 1: return 0x016e;
case 3: return m_count;
}
break;
case NAMCONB1_VSHOOT:
switch (offset)
{
case 2: return m_count << 16;
case 3: return 0x0170 << 16;
}
break;
case NAMCONB2_OUTFOXIES:
switch (offset)
{
case 0: return 0x0186;
case 1: return m_count << 16;
}
break;
case NAMCONB2_MACH_BREAKERS:
break; /* no protection? */
}
if (ENABLE_LOGGING)
logerror( "custom_key_r(%d); pc=%08x\n", offset, m_maincpu->pc() );
return 0;
} /* custom_key_r */
/***************************************************************/
u32 namconb1_state::gunbulet_gun_r(offs_t offset)
{
int result = 0;
switch (offset)
{
case 0: case 1: result = (u8)(0x0f + m_light1_y->read() * 224/255); break; /* Y (p2) */
case 2: case 3: result = (u8)(0x26 + m_light1_x->read() * 288/314); break; /* X (p2) */
case 4: case 5: result = (u8)(0x0f + m_light0_y->read() * 224/255); break; /* Y (p1) */
case 6: case 7: result = (u8)(0x26 + m_light0_x->read() * 288/314); break; /* X (p1) */
}
return result<<24;
} /* gunbulet_gun_r */
u32 namconb1_state::randgen_r()
{
return machine().rand();
} /* randgen_r */
void namconb1_state::srand_w(u32 data)
{
/**
* Used to seed the hardware random number generator.
* We don't yet know the algorithm that is used, so for now this is a NOP.
*/
} /* srand_w */
u32 namconb1_state::share_r(offs_t offset)
{
return (m_namconb_shareram[offset * 2] << 16) | m_namconb_shareram[offset * 2 + 1];
}
void namconb1_state::share_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA(m_namconb_shareram + offset * 2 + 1);
data >>= 16;
mem_mask >>= 16;
COMBINE_DATA(m_namconb_shareram + offset *2);
}
void namconb1_state::namconb1_am(address_map &map)
{
map(0x000000, 0x0fffff).rom();
map(0x100000, 0x10001f).r(FUNC(namconb1_state::gunbulet_gun_r));
map(0x1c0000, 0x1cffff).ram();
map(0x1e4000, 0x1e4003).rw(FUNC(namconb1_state::randgen_r), FUNC(namconb1_state::srand_w));
map(0x200000, 0x207fff).rw(FUNC(namconb1_state::share_r), FUNC(namconb1_state::share_w));
map(0x208000, 0x2fffff).ram();
map(0x400000, 0x40001f).rw(FUNC(namconb1_state::namconb1_cpureg_r), FUNC(namconb1_state::namconb1_cpureg_w));
map(0x580000, 0x5807ff).rw(m_eeprom, FUNC(eeprom_parallel_28xx_device::read), FUNC(eeprom_parallel_28xx_device::write));
map(0x600000, 0x61ffff).rw(m_c355spr, FUNC(namco_c355spr_device::spriteram_r), FUNC(namco_c355spr_device::spriteram_w)).share("objram");
map(0x620000, 0x620007).rw(m_c355spr, FUNC(namco_c355spr_device::position_r), FUNC(namco_c355spr_device::position_w));
map(0x640000, 0x64ffff).rw(m_c123tmap, FUNC(namco_c123tmap_device::videoram16_r), FUNC(namco_c123tmap_device::videoram16_w));
map(0x660000, 0x66003f).rw(m_c123tmap, FUNC(namco_c123tmap_device::control16_r), FUNC(namco_c123tmap_device::control16_w));
map(0x680000, 0x68000f).ram().share("spritebank32");
map(0x6e0000, 0x6e001f).r(FUNC(namconb1_state::custom_key_r)).nopw();
map(0x700000, 0x707fff).rw(m_c116, FUNC(namco_c116_device::read), FUNC(namco_c116_device::write));
}
void namconb1_state::namconb2_am(address_map &map)
{
map(0x000000, 0x0fffff).rom();
map(0x1c0000, 0x1cffff).ram();
map(0x1e4000, 0x1e4003).rw(FUNC(namconb1_state::randgen_r), FUNC(namconb1_state::srand_w));
map(0x200000, 0x207fff).rw(FUNC(namconb1_state::share_r), FUNC(namconb1_state::share_w));
map(0x208000, 0x2fffff).ram();
map(0x400000, 0x4fffff).rom().region("data", 0);
map(0x600000, 0x61ffff).rw(m_c355spr, FUNC(namco_c355spr_device::spriteram_r), FUNC(namco_c355spr_device::spriteram_w)).share("objram");
map(0x620000, 0x620007).rw(m_c355spr, FUNC(namco_c355spr_device::position_r), FUNC(namco_c355spr_device::position_w));
map(0x640000, 0x64000f).ram(); /* unknown xy offset */
map(0x680000, 0x68ffff).rw(m_c123tmap, FUNC(namco_c123tmap_device::videoram16_r), FUNC(namco_c123tmap_device::videoram16_w));
map(0x6c0000, 0x6c003f).rw(m_c123tmap, FUNC(namco_c123tmap_device::control16_r), FUNC(namco_c123tmap_device::control16_w));
map(0x700000, 0x71ffff).rw(m_c169roz, FUNC(namco_c169roz_device::videoram_r), FUNC(namco_c169roz_device::videoram_w));
map(0x740000, 0x74001f).rw(m_c169roz, FUNC(namco_c169roz_device::control_r), FUNC(namco_c169roz_device::control_w));
map(0x800000, 0x807fff).rw(m_c116, FUNC(namco_c116_device::read), FUNC(namco_c116_device::write));
map(0x900008, 0x90000f).ram().share("spritebank32");
map(0x940000, 0x94000f).ram().share("tilebank32");
map(0x980000, 0x98000f).ram().w(FUNC(namconb1_state::rozbank32_w)).share("rozbank32");
map(0xa00000, 0xa007ff).rw(m_eeprom, FUNC(eeprom_parallel_28xx_device::read), FUNC(eeprom_parallel_28xx_device::write));
map(0xc00000, 0xc0001f).r(FUNC(namconb1_state::custom_key_r)).nopw();
map(0xf00000, 0xf0001f).rw(FUNC(namconb1_state::namconb2_cpureg_r), FUNC(namconb1_state::namconb2_cpureg_w));
}
void namconb1_state::mcu_shared_w(offs_t offset, u16 data, u16 mem_mask)
{
// HACK! Many games data ROM routines redirect the vector from the sound command read to an RTS.
// This needs more investigation. nebulray and vshoot do NOT do this.
// Timers A2 and A3 are set up in "external input counter" mode, this may be related.
#if 0
if ((offset == 0x647c/2) && (data != 0))
{
data = 0xd2f6;
}
#endif
COMBINE_DATA(&m_namconb_shareram[offset]);
// C74 BIOS has a very short window on the CPU sync signal, so immediately let the '020 at it
if ((offset == 0x6000/2) && (data & 0x80))
{
m_mcu->spin_until_time(m_mcu->cycles_to_attotime(300)); // was 300
}
}
void namconb1_state::namcoc75_am(address_map &map)
{
map(0x002000, 0x002fff).rw("c352", FUNC(c352_device::read), FUNC(c352_device::write));
map(0x004000, 0x00bfff).ram().w(FUNC(namconb1_state::mcu_shared_w)).share("namconb_share");
map(0x200000, 0x27ffff).rom().region("c75data", 0);
}
uint8_t namconb1_state::port6_r()
{
return m_port6;
}
void namconb1_state::port6_w(uint8_t data)
{
m_port6 = data;
}
uint8_t namconb1_state::port7_r()
{
switch (m_port6 & 0xf0)
{
case 0x00:
return m_p4.read_safe(0xff);
case 0x20:
return m_misc->read();
case 0x40:
return m_p1->read();
case 0x60:
return m_p2->read();
default:
break;
}
return 0xff;
}
// Is this madness? No, this is Namco. They didn't have enough digital ports for all 4 players,
// so the 8 bits of player 3 got routed to the 8 analog inputs. +5V on the analog input will
// register full scale, so it works...
template <int Bit>
u16 namconb1_state::dac_bit_r()
{
return (m_p3.read_safe(0xff) << (7 - Bit)) & 0x80;
}
/****************************************************************************/
static INPUT_PORTS_START( gunbulet )
PORT_START("MISC")
PORT_DIPUNUSED_DIPLOC(0x01, 0x01, "SW1: 2")
PORT_SERVICE_DIPLOC(0x02, 0x02, "SW1: 1")
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_DIPNAME( 0x40, 0x40, "Test switch" )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_START("P1")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
PORT_START("P2")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
PORT_START("LIGHT0_X")
PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(4)
PORT_START("LIGHT0_Y")
PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(4)
PORT_START("LIGHT1_X")
PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_X ) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(4) PORT_PLAYER(2)
PORT_START("LIGHT1_Y")
PORT_BIT( 0xff, 0x80, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(4) PORT_PLAYER(2)
INPUT_PORTS_END
static INPUT_PORTS_START( namconb1 )
PORT_START("P1")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
PORT_START("P2")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
PORT_START("P3")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START3 )
PORT_START("P4")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
PORT_START("MISC")
PORT_DIPNAME( 0x01, 0x01, "Freeze Screen" ) PORT_DIPLOCATION("SW1: 2")
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_SERVICE_DIPLOC(0x02, 0x02, "SW1: 1")
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN4 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN3 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_DIPNAME( 0x40, 0x40, "Test switch" )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
INPUT_PORTS_END
/****************************************************************************/
void namconb1_state::init_nebulray()
{
m_gametype = NAMCONB1_NEBULRAY;
m_update_to_line_before_posirq = true; // needed or there is a bad line on the right of the screen, and some stars don't scroll correctly
} /* nebulray */
void namconb1_state::init_gslgr94u()
{
m_gametype = NAMCONB1_GSLGR94U;
} /* gslgr94u */
void namconb1_state::init_gslgr94j()
{
m_gametype = NAMCONB1_GSLGR94J;
} /* gslgr94j */
void namconb1_state::init_sws95()
{
m_gametype = NAMCONB1_SWS95;
} /* sws95 */
void namconb1_state::init_sws96()
{
m_gametype = NAMCONB1_SWS96;
} /* sws96 */
void namconb1_state::init_sws97()
{
m_gametype = NAMCONB1_SWS97;
} /* sws97 */
void namconb1_state::init_gunbulet()
{
m_gametype = NAMCONB1_GUNBULET;
} /* gunbulet */
void namconb1_state::init_vshoot()
{
m_gametype = NAMCONB1_VSHOOT;
} /* vshoot */
void namconb1_state::init_machbrkr()
{
m_gametype = NAMCONB2_MACH_BREAKERS;
}
void namconb1_state::init_outfxies()
{
m_gametype = NAMCONB2_OUTFOXIES;
}
/***************************************************************/
void namconb1_state::machine_reset()
{
m_pos_irq_level = 0;
m_unk_irq_level = 0;
m_vbl_irq_level = 0;
}
/***************************************************************/
void namconb1_state::namconb1(machine_config &config)
{
M68EC020(config, m_maincpu, MASTER_CLOCK / 2);
m_maincpu->set_addrmap(AS_PROGRAM, &namconb1_state::namconb1_am);
NAMCO_C75(config, m_mcu, MASTER_CLOCK / 3);
m_mcu->set_addrmap(AS_PROGRAM, &namconb1_state::namcoc75_am);
m_mcu->p6_in_cb().set(FUNC(namconb1_state::port6_r));
m_mcu->p6_out_cb().set(FUNC(namconb1_state::port6_w));
m_mcu->p7_in_cb().set(FUNC(namconb1_state::port7_r));
m_mcu->an7_cb().set(FUNC(namconb1_state::dac_bit_r<7>));
m_mcu->an6_cb().set(FUNC(namconb1_state::dac_bit_r<3>));
m_mcu->an5_cb().set(FUNC(namconb1_state::dac_bit_r<2>));
m_mcu->an4_cb().set(FUNC(namconb1_state::dac_bit_r<1>));
m_mcu->an3_cb().set(FUNC(namconb1_state::dac_bit_r<0>));
m_mcu->an2_cb().set(FUNC(namconb1_state::dac_bit_r<4>));
m_mcu->an1_cb().set(FUNC(namconb1_state::dac_bit_r<5>));
m_mcu->an0_cb().set(FUNC(namconb1_state::dac_bit_r<6>));
EEPROM_2816(config, "eeprom");
TIMER(config, "scantimer").configure_scanline(FUNC(namconb1_state::scantimer), "screen", 0, 1);
// has to be 60 hz or music will go crazy in nebulray, vshoot, gslugrs*
TIMER(config, "mcu_irq0").configure_periodic(FUNC(namconb1_state::mcu_irq0_cb), attotime::from_hz(60));
TIMER(config, "mcu_irq2").configure_periodic(FUNC(namconb1_state::mcu_irq2_cb), attotime::from_hz(60));
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_raw(MASTER_CLOCK / 8, 384, 0, 288, 264, 0, 224);
m_screen->set_screen_update(FUNC(namconb1_state::screen_update_namconb1));
m_screen->screen_vblank().set(FUNC(namconb1_state::screen_vblank));
m_screen->set_palette(m_c116);
NAMCO_C355SPR(config, m_c355spr);
m_c355spr->set_screen(m_screen);
m_c355spr->set_palette(m_c116);
m_c355spr->set_scroll_offsets(0x26, 0x19);
m_c355spr->set_tile_callback(namco_c355spr_device::c355_obj_code2tile_delegate(&namconb1_state::NB1objcode2tile, this));
m_c355spr->set_palxor(0x0);
m_c355spr->set_buffer(2); // triple buffered
m_c355spr->set_color_base(0);
m_c355spr->set_draw_2_lists(false); // prevents bad tile on top left of vshoot during certain scenes