| Power | Energy |
|---|---|
| Instantaneous draw - V* I | Total power draw over time |
| Requirement - deliver I at V and $\Delta$I at V | Depends on the available capacity of the power source |
| Heat generated | Form factor and size of the battery |
| Increasing Power Consumption | Increasing Energy Consumption |
|---|---|
| Heat generated in the IC/system increases | Finite packed resource depletes faster |
| Requirement of better heat sink/fan | Cost increases with energy consumption |
| Frequency gets capped resulting in decrease in performance | Systemic Metric |
| Material degradation |
The power and energy consumption in an IC or a system impacts the complete economics of the product. The factors affected are mentioned below,
- Performance
- Cost
- Weight
- Form factor
- Overall functionality
- Safety
- Usage of the system (Portable or mobile)
In the below example, a case study is done to know if the improvement of performance can lead to increase or decrease in power consumption.
Consider a a display monitor having 1920x1080 (~2M pixels) processed at 120Hz/60Hz
Case 1 - Consider a 1.8V processor at 120Hz, 240Mhz
The power consumption = 1.8^2 * 240 = 3.24 W
Case 2 - Consider a 1.2V processor at 60Hz, 120Mhz
The power consumption = 1.2^2 * 120Mhz = 1.44W
Improving the performance does leads to higher power consumption.
| Portable | Mobile | Mobility |
|---|---|---|
| Needs electricity and could run on battery | Runs on battery | change in service and uses cases in a mobile |
| Ex Laptop | Eg Smartphone, Tablet | Phone with 4G/5G services |
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Case study 1 - Galaxy note explosion issue
Some of the main reasons are due to bad design of battery electrodes and insufficent insulation in packaging. https://www.bbc.com/news/business-38714461
The below image shows that the negative electrodes in the battery was deflected in the upper right corner due to insufficient space leading to shorting of the electrodes.
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Case study 2 - CPU Fan specifications An CPU fan used for cooling the processor and its specification is described in the image below,
The specification describe the following
-
Operating voltage of the device - 12V
-
The maximum wattage of the CPU to which the Fan can be mounted.
-
Thermal resistance of the device. A lower thermal resistance indicate that device offers less resistance to heat flow and has the ability to cool CPU faster.
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Case study 3 - Apple iphone 6 battery issues
The main reason stated by apple for slowing down the performance of iphone 6 was to compensate the degration and lifetime of battery. https://www.theverge.com/2017/12/28/16827248/apple-iphone-battery-replacement-price-slow-down-apology
Basic concepts are refreshed
| Parameter | Definition |
|---|---|
| Voltage | Measure of the electric field or force |
| Current | Rate of flow of charges under an electric field |
| R,L and C | That impedes the current or changes the state of Voltage |
The different operating conditions in a CMOS combinational and sequential circuit based on the rise and fall time are mentioned below,
| Parameter | Combinational Logic | Sequential Logic |
|---|---|---|
| Shutdown | OFF | OFF |
| Standby | ON | Reads are allowed no writes |
| Active | ON | Read and write are allowed |
The below figure is an example of a CMOS inverter with Voltage nodes that can be used for a low power design
| Name | Voltage Nodes |
|---|---|
| Power gating | SLPP, SLPN |
| Voltage scaling | VDD,VSS |
| Back Biasing | VBBP,VBBN |
| State Retention | VRET |
The various techniques for voltage control in a CMOS IC design are descirbed in the below figure ,
| Name | Description |
|---|---|
| Multi Vdd (MVV) | Divide the blocks into static multiple voltages |
| MTCMOS power gating | Shut down logic not in use by placing a switch (power gating transistor) |
| Power gating with state retention | Variant of power gating that to retain the state |
| Dynamic or adaptive Voltage frequency scaling (DVS, DVFS, AVS, AVFS) | VRET |
| Variable Vth | Done by Back bias of PMOS/NMOS (for memory) |
| Low VDD standby | Blocks not in use reduce the voltage to retain the state |
Some of the multi-voltage control techniques used in various applications are listed below,
| Application | Concerns | Mult-Voltage control techniques |
|---|---|---|
| Audio | Battery life | Power Gating |
| Video | Active, Idle | DVFS, Standby, Power Gating |
| GPS | Response, Battery life | Power Gating |
| W/S. Server | Perfomance, Heat | DVFS, Multi-VDD |
| Laptop | Heat, port density | DVFS,standby, Power gating |
| Networking | Heat, port density | Multi-VDD, Standby, Power gating |
| USB | Peak Power | Multi-VDD |
The total power dissipations in a CMOS is mainly divided into static power dissipation and dynamic power dissipation given by the below equations,
The static power dissipation is the first part of the sum and the dynamic power is defined by the second part of the sum.
During operation of an application in a mobile phone for ex, various activities are invoked to utilise the hardware resources to perform the function.
An example of hardware resources used during a video-call applicaiton in a Mobile processor is shown below,
The arrow with the red line shows the direction of resources that are used during a video call application.
The application mostly uses a gsm module, baseband PLL, Mobile video interface, memory control and system cpu.
Some blocks such as serial IOs, DFT, WCDMA are not used during the video call application and hence it can be turned off to conserve power.
The below charts shows the distribution of power consumption under various application and scenraios,
Reference - Power Consumption Breakdown on a Modern Laptop - Aqeel Mahesri and Vibhore Vardhan
From the above power analysis it can be seen that the power consumption is greatly depend on the activity in the laptop.
For example PCMark CPU test has the highest power consumption in comparison or Audio CD playback modes.
Some more analysis on idle state with dynamic voltage scaling (DVS) in idle mode for different brightness shows that the power in the rest of the laptop system, CPU power and LCD backlight dominates the power distribution chart.
The most important parameters that needs to be consider during balancing the power management and low power design are described below,
| Parameter | Description |
|---|---|
| Density | Defined by Power/Area indicates thermal power dissipated over an area. The power consumed is a function of junction temperature. |
| Delivery | Managing the current I and change in current dI for the operating voltage of the IC |
| Leakage | Leakage power is due power consumption of the subthreshold current during idle or active state in the transistor. Leakage increases with gate size. |
| Reliability | Reach the constraint to be within material degration limit by electromigration and Average power over time |
The schematic of the buffer circuit used for this test is shown below,
The voltage level outputs of the ideal buffer circuit with V1 and V2 = 1.8 is tabulated below - the voltage level 1.8 is HIGH(1) and 0 is LOW(0),
| IN1 | OUT1 | OUT2 |
|---|---|---|
| 1.8(H) | 0(L) | 1.8(H) |
| 0(L) | 1.8(H) | 0(L) |
In this exercise, the supply voltage of the second inverter V2 is set to 1.8V and the voltage of the first inverter V1 is increased from 0.7V to 1.8V in steps of 0.1V
The spice simulation is done using ngspice with the below command,
The output obtained from ngspice simulation is shown below,
The waveforms for the different voltage nodes V2, In1, V1, Out1, Out2 are shown in the below figure,
From the above exercise, it is seen that voltage level of the first inverter V1 plays an important role in the output obtained Out1.
Until a timestamp of 8ns, the Voltage level V1 of the first inverter is not high enough to obtain a logic high at the output Out1 when the input in1 is low
After 8ns the output of the first inverter reach a sufficient voltage level to obtained an output high when the in1 is low.
The schematic of the NAND circuit used for this test is shown below,
The voltage level outputs of the ideal NAND circuit with V1 = 1.8 with inputs V2 and V3 is tabulated below - the voltage level 1.8 is HIGH(1) and 0 is LOW(0),
| V2 | V3 | OUT |
|---|---|---|
| 0(L) | 0(L) | 1.8(H) |
| 0(L) | 1.8(H) | 1.8(H) |
| 1.8(H) | 0(L) | 1.8(H) |
| 1.8(H) | 1.8(H) | 0(L) |
In this exercise, the supply voltage, input voltage and output voltage are varied in steps of 0.1V
The waveforms for the different voltage nodes V1, V2, V3, Out are shown in the below figure,
From the above exercise, it is seen that the output voltage level of 1.8V(H) is not reached upto a timestamp of 32ns.
The effect of the supply voltage, voltage levels of the input on the actual output can be seen in this lab exercise.