A 2-day workshop in the analysis and implementation of PLL in skywater 130nm OpenPDK is conducted by VSD.
The report presents the activities done during the two-day workshop.
A Phase Locked Loop generates a precise clock signal,
The components of the PLL are described in the block diagram below,
| Components | Funtionality |
|---|---|
| Phase Frequency Detector (PFD) | Comparison between the phase difference between Feedback signal and Reference signal |
| Charge Pump (CP) | Converts the digital output of the PFD to analog signal |
| Low Pass Filter(LP) | Smoothen the charge pump output signal |
| Voltage Control Oscillator (VCO) | Onchip ring oscillator controlled by Voltage |
| Frequency Divider (FD) | Output frequencies that is multiple of the reference clock signal |
The circuit implementation, simulation and layout of the components of the PLL will be discussed in Day 2.
The PLL specification are described below,
| Specification | Value |
|---|---|
| Corner | TT (Typical) |
| Supply Voltage | 1.8V |
| Temperature | 25 DegC (Room Temperature) |
| Modes | VCO Mode and PLL mode |
| Input Frequency | Fmin = 5Mhz and Fmax = 12.5Mhz |
| Mutiplier | Form factor and size of the battery |
| Jitter (RMS) | <~20ns |
| Duty Cycle | 50% |
The tools and the setup details used for the development of the PLL are given below,
| Tool | Description | Setup details |
|---|---|---|
| Ngspice | Circuit Simulation | sudo apt-get install ngspice |
| Magic | Layout Design | Setup described in https://opencircuitdesign.com/magic |
The implementation of the individual components of the PLL are described in this section.
The frequency divider consists of a toggle flip flop.
The output of the toggle flip flop will be half of input frequency signal.
The circuit diagram of the toggle flip flop is shown below,
The spice file for the simulation of the Frequency divider is written as below,
.include sky130nm.lib
xm1 1 2 3 1 sky130_fd_pr__pfet_01v8 l=150n w=720n
xm2 0 2 3 0 sky130_fd_pr__nfet_01v8 l=150n w=360n
xm3 3 Clkb 4 1 sky130_fd_pr__pfet_01v8 l=150n w=420n
xm4 3 Clk 4 0 sky130_fd_pr__nfet_01v8 l=150n w=840n
xm7 1 4 5 1 sky130_fd_pr__pfet_01v8 l=150n w=720n
xm8 0 4 5 0 sky130_fd_pr__nfet_01v8 l=150n w=360n
xm9 5 Clk 6 1 sky130_fd_pr__pfet_01v8 l=150n w=420n
xm10 5 Clkb 6 0 sky130_fd_pr__nfet_01v8 l=150n w=640n
xm11 1 6 2 1 sky130_fd_pr__pfet_01v8 l=150n w=720n
xm12 0 6 2 0 sky130_fd_pr__nfet_01v8 l=150n w=360n
xm13 1 Clk Clkb 1 sky130_fd_pr__pfet_01v8 l=150n w=720n
xm14 0 Clk Clkb 0 sky130_fd_pr__nfet_01v8 l=150n w=360n
v1 1 0 1.8
v2 Clk 0 PULSE 0 1.8 1n 6p 6p 5ns 10ns
c1 6 0 10f
.control
tran 0.1ns 0.2us
plot v(6) v(Clk)+2
.endc
.endThe command to run the spice file
ngspice FD.cirThe output of the frequency divider is shown below,
From the above result, it can be seen that the output frequency in red is half the input frequency in blue.
The layout of the Frequency Divider is done using magic.
The developed freqeuncy divider circuit can be opened using magic using the following commands,
magic -T sky130A.tech FD.mag
The charge pump circuit converts the digital output from the Phase frequency detector to analog output to control the voltage controlled oscillator.
The citcuit implementation consists of a current steering circuit implemented using mosfets as shown in the circuit below.
The mosfet transistor pair at the top and bottom of the circuit form the current sources in the design.
During the time when UP is active the output voltage increases.The output voltage decreases during the time when DOWN signal is active.
The obtained results using circuit simulation in ngspice is shown below,
From the output graphs, it is seen that the charge pump output signal increases with UP signal active.
The layout of the charge pump circuit is shown below,
The voltage control oscillator consists of a Ring oscillator having a series odd number of inverters.
In the below circuit, the ring oscillator are implement with 3 inverter - 1st inverter: M3, M6 , 2nd inverter: M4, M7 and 3rd inverter: M5,M8
By using a current starving mechanism, the current through the ring oscillator can be controlled to obtain different output frequency.
The input control voltage Vcntrl controls the current through the ring oscillator.
This results in the change in the frequency of the ring oscillator.
The circuit is simulated in ngspice.
The results show that the oscillation have a voltage output with full swing from 0 to 1.8V.
The layout of the charge pump circuit is shown below,
The Phase frequency detector generates output as UP signal if the VCO signal is laging the reference signal and a DOWN signal if the the output of the VCO is leading the reference signal.
The UP and DOWN signal determines if the output frequency of the VCO needs to be increased or decreased.
The Phase frequency detector is implement using the below circuit,
The circuit is simulated in ngspice. The phase difference of the reference and the feedback signal is 6ns
The circuit is able to detect the small difference between the reference and feedback signal.
The layout of the Phase frequency detector in magic is shown below,
In the next step, a combined simulation of all the circuit components are done in ngspice.
The obtained output from ngspice is shown below,
The frequency division is shown in signal with pink(4th row), green(5th row) and orange(6th row).
The reference signal is in red and the feedback signal is in blue show slight fluctuation.
The layout of the complete PLL in magic is shown below,
The parasitic capacitance and resistance are extracted from the layout and post layout spice analysis is done.
The commands are executed in magic command window as shown below,
The obtained output from ngspice for the post layout simulation is shown below,
The result shows that the circuit can detect phase difference of 1ns.
The layout of the charge pump circuit and the Voltage control oscillator using metal1 can be done in magic.
The combined layout of the charge pump circuit and the VCO is shown below,
The Caravel SoC is a PicoRV32 RISC based SoC provided by Google-Skywater OpenPDK programme.
The user project area is about 2.92mm x 3.52mm with 36 GPIOs as shown in the block diagram below,
In the next step, the PLL layout is added in the user project area.
The user_analog_project_wrapper_empty.gds file is downloaded from the efabless github https://github.com/efabless/caravel-lite/tree/main/gds
The Pins are located on the corner of the block. In the below image the I/O pins can be found on the bottom left corner.
The PLL layout is placed as an instance on the upper left corner close to the analog IO pin.
A metal 2 and metal 3 contact is done between the output pin of the PLL block and the analog IO pin.
The final layout of PLL integrated with the caravel SOC is shown below,
Github of the PLL used in this workshop - https://github.com/lakshmi-sathi/avsdpll_1v8
Lakshmi Sathi - Course Instructor
Kunal Ghosh - VSD India Pvt Ltd