- 👋 Hello! I’m @mankelly.
- 👀 I’m interested in Embedded System Design using Verilog/SystemVerilog and Embedded System Software development.
- 🌱 I’m currently learning CPU design and VHDL to expand my HDL library.
- 💞️ I’m looking to collaborate on Embedded Systems projects.
- 📫 How to reach me? Contact me on LinkedIn!
🎯
Focusing
Block or Report
Block or report mankelly
Report abuse
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
Report abusePinned
-
-
VerilogProjects
VerilogProjects PublicAll projects that utilize the Verilog & SystemVerilog HDL's.
-
-
-
-
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.