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mapkkkk committed Jan 5, 2024
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17 changes: 15 additions & 2 deletions README.md
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# hust-cse-crypto-verilog
华中科技大学网络空间安全学院密码工程学基础2023
# hust-cse-crypto-verilog

**华中科技大学网络空间安全学院密码工程学基础2023**

*powered by mxy*

------

*First，用过本课程库的请star一下~*

四个实验分别在四个文件夹里，请使用iverilog编译，先编译代码本体如`aes.v`，再编译`test bench`如`tb_aes.v`。

编译工具链推荐使用`vscode`+`iverilog`，具体安装方法请自行搜索(知乎上有)。

需要烧录在`FPGA`板子上的，请使用`vivado`生成比特流（课程第一节课会讲），同时，仿真占比90%，纯仿真使用`vscode`即可。
179 changes: 179 additions & 0 deletions 实验1(UART)/Computation.v
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`timescale 1ns / 1ps

module Computation(
Clk ,
Rst ,
In_enable ,
Out_done ,
// FIFO
In_rcv_dout ,
Out_rcv_rd_en ,
Out_snd_din ,
Out_snd_wr_en
);

//---------------------------------------------------------------------------------------
// Parameter
//---------------------------------------------------------------------------------------
parameter TCQ = 1 ;
//FSM-------------------------------------------------------------------
parameter STA_IDLE = 4'h0 ;
parameter STA_READING = 4'h1 ;
parameter STA_ROUND = 4'h2 ;
parameter STA_ROUND_DONE = 4'h3 ;
parameter STA_WRITING = 4'h4 ;
parameter STA_COMPUTING_DONE = 4'h5 ;

//---------------------------------------------------------------------------------------
// Port Define
//---------------------------------------------------------------------------------------
input wire Clk ;
input wire Rst ;
input wire In_enable ;
output wire Out_done ;
// FIFO
input wire [31:0] In_rcv_dout ;
output wire Out_rcv_rd_en ;
output wire [31:0] Out_snd_din ;
output wire Out_snd_wr_en ;

//---------------------------------------------------------------------------------------
// Signals
//---------------------------------------------------------------------------------------
reg out_done ;
reg out_rcv_rd_en ;
reg [31:0] out_snd_din ;
reg out_snd_wr_en ;

reg [31:0] rcv_dout ;
reg [31:0] tmp ;
reg [7:0] cnt_round ;

//---------------------------------------------------------------------------------------
// Instance
//---------------------------------------------------------------------------------------
//CompIla InstCompIla(
// .clk (Clk ), // input wire clk
// .probe0 (In_enable ), // input wire [0:0] probe0
// .probe1 (Out_done ), // input wire [0:0] probe1
// .probe2 (In_rcv_dout ), // input wire [31:0] probe2
// .probe3 (Out_rcv_rd_en ), // input wire [0:0] probe3
// .probe4 (Out_snd_din ), // input wire [31:0] probe4
// .probe5 (Out_snd_wr_en ), // input wire [0:0] probe5
// .probe6 (curr_state ), // input wire [7:0] probe6
// .probe7 (cnt_round ) // input wire [7:0] probe7
//);

//---------------------------------------------------------------------------------------
// Function Codes
//---------------------------------------------------------------------------------------
assign Out_done = out_done;
assign Out_rcv_rd_en = out_rcv_rd_en;
assign Out_snd_din = out_snd_din;
assign Out_snd_wr_en = out_snd_wr_en;

//---------------------------------------------------------------------------------------
// FSM
//---------------------------------------------------------------------------------------
reg [7:0] curr_state ;
reg [7:0] next_state ;

//State Tranfer
always @(posedge Clk) begin
if(Rst == 1'b1)
curr_state <= #TCQ STA_IDLE;
else
curr_state <= #TCQ next_state;
end

//Calculate the next state
always @( * ) begin
case(curr_state)
STA_IDLE : begin
if(In_enable)
next_state = STA_READING;
else
next_state = STA_IDLE;
end

STA_READING : begin
next_state = STA_ROUND;
end

STA_ROUND : begin
next_state = STA_ROUND_DONE;
end

STA_ROUND_DONE : begin
next_state = STA_WRITING;
end

STA_WRITING : begin
if(cnt_round < 8'd4)
next_state = STA_READING;
else if(cnt_round == 8'd4)
next_state = STA_COMPUTING_DONE;
end

STA_COMPUTING_DONE : begin
next_state = STA_IDLE;
end

default : begin
next_state = STA_IDLE;
end
endcase
end

//state output
always @(posedge Clk) begin
if(Rst == 1'b1) begin
out_rcv_rd_en <= #TCQ 1'b0;
out_snd_wr_en <= #TCQ 1'b0;
out_snd_din <= #TCQ 32'd0;
rcv_dout <= #TCQ 32'd0;
out_done <= #TCQ 1'b0;
cnt_round <= #TCQ 8'd0;
end

else case(curr_state)
STA_IDLE : begin
out_rcv_rd_en <= #TCQ 1'b0;
out_snd_wr_en <= #TCQ 1'b0;
out_snd_din <= #TCQ 32'd0;
rcv_dout <= #TCQ 32'd0;
out_done <= #TCQ 1'b0;
cnt_round <= #TCQ 8'd0;
end

STA_READING : begin
out_snd_wr_en <= #TCQ 1'b0;
out_snd_din <= #TCQ 32'd0;
out_rcv_rd_en <= #TCQ 1'b1;
rcv_dout <= #TCQ In_rcv_dout;
end

STA_ROUND : begin
out_rcv_rd_en <= #TCQ 1'b0;
tmp <= #TCQ {rcv_dout[7:0], rcv_dout[15:8], rcv_dout[23:16], rcv_dout[31:24]};
end

STA_ROUND_DONE : begin
cnt_round <= #TCQ cnt_round + 8'd1;
end

STA_WRITING : begin
out_snd_wr_en <= #TCQ 1'b1;
out_snd_din <= #TCQ tmp;

end

STA_COMPUTING_DONE : begin
out_snd_wr_en <= #TCQ 1'b0;
out_done <= #TCQ 1'b1;
end
endcase
end

endmodule

161 changes: 161 additions & 0 deletions 实验1(UART)/Top.v
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`timescale 1ns / 1ps

module Top(
Clk_p ,
Clk_n ,
//Rx and Tx
In_rx ,
Out_tx
);
//---------------------------------------------------------------------------------------
// Parameter
//---------------------------------------------------------------------------------------
parameter TCQ = 1 ;

//---------------------------------------------------------------------------------------
// Port Define
//---------------------------------------------------------------------------------------
input wire Clk_p ;
input wire Clk_n ;
//Rx and Tx
input wire In_rx ;
output wire Out_tx ;

//---------------------------------------------------------------------------------------
// Signals
//---------------------------------------------------------------------------------------
//ClkWid
wire clk200m ;
wire clk100m ;
wire clk50m ;
wire locked ;
//RcvFifo
wire [7:0] rcv_din ;
wire rcv_wr_en ;
wire rcv_full ;
wire [5:0] rcv_wr_data_count ;
wire [31:0] rcv_dout ;
wire rcv_rd_en ;
wire rcv_empty ;
wire [3:0] rcv_rd_data_count ;
//SndFifo
wire [31:0] snd_din ;
wire snd_wr_en ;
wire snd_full ;
wire [3:0] snd_wr_data_count ;
wire [7:0] snd_dout ;
wire snd_rd_en ;
wire snd_empty ;
wire [5:0] snd_rd_data_count ;
//Computation
wire comp_enable ;
wire comp_done ;

//---------------------------------------------------------------------------------------
// Instance
//---------------------------------------------------------------------------------------
IBUFGDS InstClkTrans
(
.O(clk200m),
.I(Clk_p),
.IB(Clk_n)
);

ClkWiz InstClkWiz(
.clk_out100m (clk100m ), // output clk_out100m
.clk_out50m (clk50m ), // output clk_out50m
.clk_in200m (clk200m ), // input clk_in100m
.locked (locked )
);

Uart InstUart(
.Clk (clk100m ),
.Rst (!locked ),
//Rx and Tx
.In_rx (In_rx ),
.Out_tx (Out_tx ),
//FIFO
.In_rcv_wr_data_count (rcv_wr_data_count ),
.In_rcv_full (rcv_full ),
.Out_rcv_wr_en (rcv_wr_en ),
.Out_rcv_din (rcv_din ),
.In_snd_rd_data_count (snd_rd_data_count ),
.In_snd_empty (snd_empty ),
.Out_snd_rd_en (snd_rd_en ),
.In_snd_dout (snd_dout ),
//Computation
.In_comp_done (comp_done ),
.Out_comp_enable (comp_enable )
);

RcvFifo InstRcvFifo(
.rst (!locked ), // input wire rst
.wr_clk (clk100m ), // input wire wr_clk
.rd_clk (clk50m ), // input wire rd_clk
.din (rcv_din ), // input wire [7 : 0] din
.wr_en (rcv_wr_en ), // input wire wr_en
.rd_en (rcv_rd_en ), // input wire rd_en
.dout (rcv_dout ), // output wire [31 : 0] dout
.full (rcv_full ), // output wire full
.empty (rcv_empty ), // output wire empty
.rd_data_count (rcv_rd_data_count ), // output wire [3 : 0] rd_data_count
.wr_data_count (rcv_wr_data_count ) // output wire [5 : 0] wr_data_count
);

SndFifo InstSndFifo(
.rst (!locked ), // input wire rst
.wr_clk (clk50m ), // input wire wr_clk
.rd_clk (clk100m ), // input wire rd_clk
.din (snd_din ), // input wire [31 : 0] din
.wr_en (snd_wr_en ), // input wire wr_en
.rd_en (snd_rd_en ), // input wire rd_en
.dout (snd_dout ), // output wire [7 : 0] dout
.full (snd_full ), // output wire full
.empty (snd_empty ), // output wire empty
.rd_data_count (snd_rd_data_count ), // output wire [5 : 0] rd_data_count
.wr_data_count (snd_wr_data_count ) // output wire [3 : 0] wr_data_count
);

Computation InstComputation(
.Clk (clk50m ),
.Rst (!locked ),
.In_enable (comp_enable ),
.Out_done (comp_done ),
//FIFO
.In_rcv_dout (rcv_dout ),
.Out_rcv_rd_en (rcv_rd_en ),
.Out_snd_din (snd_din ),
.Out_snd_wr_en (snd_wr_en )
);
//ILA
TopIla InstTopIla(
.clk (clk100m ), // input wire clk
.probe0 (comp_enable ), // input wire [0:0] probe0
.probe1 (comp_done ), // input wire [0:0] probe1
.probe2 (rcv_dout ), // input wire [31:0] probe2
.probe3 (rcv_rd_en ), // input wire [0:0] probe3
.probe4 (snd_din ), // input wire [31:0] probe4
.probe5 (snd_wr_en ), // input wire [0:0] probe5
.probe6 (snd_empty ), // input wire [0:0] probe6
.probe7 (snd_rd_data_count ) // input wire [5:0] probe7
//.probe8 ( ), // input wire [0:0] probe8
//.probe9 ( ), // input wire [0:0] probe9
//.probe10 ( ), // input wire [0:0] probe10
//.probe11 ( ), // input wire [0:0] probe11
//.probe12 ( ), // input wire [0:0] probe12
//.probe13 ( ), // input wire [0:0] probe13
//.probe14 ( ), // input wire [0:0] probe14
//.probe15 ( ) // input wire [0:0] probe15
);
//---------------------------------------------------------------------------------------
// Function Codes
//---------------------------------------------------------------------------------------


//---------------------------------------------------------------------------------------
// FSM
//---------------------------------------------------------------------------------------


endmodule

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