Add rte instruction

Resets ProcessingState back to Normal

Closes #41

src/cpu/ops/handlers.rs

@@ -1568,6 +1568,8 @@ pub const OP_ROXR_16_AW      : u32 = OP_SHIFT | SHIFT_RIGHT | WORD_SIZED | ROTX_
 pub const OP_ROXR_16_AL      : u32 = OP_SHIFT | SHIFT_RIGHT | WORD_SIZED | ROTX_MEM_SHIFT | OPER_AL;
 
 // Put constants for RTE here
+pub const OP_RTE_32 : u32 = 0b0100111001110011;
+
 // Put constants for RTR here
 // Put constants for RTS here
 
@@ -3270,6 +3272,8 @@ fn generate_optable() -> Vec<OpcodeHandler> {
         op_entry!(MASK_EXACT, OP_ROXR_16_AL, roxr_16_al),
 
         // Put op-entries for RTE here
+        op_entry!(MASK_EXACT, OP_RTE_32, rte_32),
+
         // Put op-entries for RTR here
         // Put op-entries for RTS here
         //
@@ -4184,4 +4188,8 @@ mod tests {
     fn correctly_defined_op_stop() {
         assert_eq!(0x4e72, OP_STOP);
     }
+    #[test]
+    fn correctly_defined_op_rte_32() {
+        assert_eq!(0x4e73, OP_RTE_32);
+    }
 }

src/cpu/ops/mod.rs

@@ -1,5 +1,5 @@
 #![macro_use]
-use super::{Core, Cycles, Result, EXCEPTION_CHK, EXCEPTION_ZERO_DIVIDE};
+use super::{Core, Cycles, Result, ProcessingState, EXCEPTION_CHK, EXCEPTION_ZERO_DIVIDE};
 use super::Exception::*;
 
 mod common;
@@ -2816,6 +2816,21 @@ roxr_16!(roxr_16_aw, ea_aw_16,    16);
 roxr_16!(roxr_16_al, ea_al_16,    20);
 
 // Put implementation of RTE ops here
+pub fn rte_32(core: &mut Core) -> Result<Cycles> {
+    if core.s_flag != 0 {
+        let new_sr = core.pop_16();
+        let new_pc = core.pop_32();
+        core.jump(new_pc);
+        core.sr_to_flags(new_sr);
+
+        core.processing_state = ProcessingState::Normal;
+
+        Ok(Cycles(20))
+    } else {
+        Err(PrivilegeViolation(core.ir, core.pc.wrapping_sub(2)))
+    }
+}
+
 // Put implementation of RTR ops here
 // Put implementation of RTS ops here
 

src/musashi.rs

@@ -1951,6 +1951,8 @@ mod tests {
     qc!(MASK_EXACT, OP_ROXR_16_AL, qc_roxr_16_al);
 
     // Put qc for RTE here
+    qc8!(MASK_EXACT, OP_RTE_32, qc_rte_32);
+
     // Put qc for RTR here
     // Put qc for RTS here