Fog conditionals are now complete! Both conditional and unconditional…

… jumps now work. FetchByte was leaving garbage in the upper bytes of the result 64-bit word. Fixed some comments. Fixed the indexing used by FetchByte, which was indexing by 8s instead of by 1s. Disassembler now handles the added instructions.
martinmcclure · Sep 29, 2012 · 9b804d7 · 9b804d7
1 parent 2c760bc
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diff --git a/packages/Mist.package/FogTests.class/class/isB.st b/packages/Mist.package/FogTests.class/class/isB.st
@@ -6,7 +6,7 @@ isB
 
 	^ Fog
 		program:
-			{(Fog breakpoint).
+			{"(Fog breakpoint)."
 			(Fog
 				variableScope:
 					{'termiosPtr'.

diff --git a/packages/Mist.package/FogTests.class/methodProperties.json b/packages/Mist.package/FogTests.class/methodProperties.json
@@ -3,7 +3,7 @@
 		"consume1" : "MartinMcClure 9/13/2012 17:09",
 		"echo1" : "MartinMcClure 9/13/2012 17:07",
 		"fortyTwo" : "MartinMcClure 9/13/2012 17:05",
-		"isB" : "MartinMcClure 9/28/2012 22:53",
+		"isB" : "MartinMcClure 9/29/2012 12:30",
 		"print7" : "MartinMcClure 9/13/2012 17:03",
 		"printH" : "MartinMcClure 9/13/2012 17:01",
 		"threePlusFour" : "MartinMcClure 9/13/2012 16:58" },

diff --git a/packages/Mist.package/FogX64FetchByteNode.class/instance/assignOutputVariableAvoiding..st b/packages/Mist.package/FogX64FetchByteNode.class/instance/assignOutputVariableAvoiding..st
@@ -0,0 +1,9 @@
+x64-compiling-pass1
+assignOutputVariableAvoiding: siblingClobbered
+	"Because I clobber my output's generationLocation before consuming my inputs (to clear the upper bytes), 
+	I must avoid my children's consumptionLocations"
+
+	| allClobbered |
+	allClobbered := siblingClobbered copy.
+	children do: [ :childVar | allClobbered add: childVar consumptionLocation ].
+	super assignOutputVariableAvoiding: allClobbered
diff --git a/packages/Mist.package/FogX64FetchByteNode.class/instance/emitOpTo..st b/packages/Mist.package/FogX64FetchByteNode.class/instance/emitOpTo..st
@@ -1,9 +1,11 @@
 x64-compiling-pass2
 emitOpTo: codeStream
-	"Base and index must be in registers, result must be in a register."
+	"Base and index must be in registers, result must be in a register. 
+	Must clear the destination register first, or the high-order bits could be anything."
 
 	| baseLoc indexLoc destLoc |
 	baseLoc := self base consumptionLocation.
 	indexLoc := self index consumptionLocation.
 	destLoc := parent generationLocation.
+	codeStream movIntConstant: 0 to: destLoc. "Better to xor with self here."
 	codeStream movByteFromAddressIn: baseLoc plusIndexIn: indexLoc toRegister: destLoc
diff --git a/packages/Mist.package/FogX64FetchByteNode.class/methodProperties.json b/packages/Mist.package/FogX64FetchByteNode.class/methodProperties.json
@@ -2,5 +2,6 @@
 	"class" : {
 		 },
 	"instance" : {
-		"emitOpTo:" : "MartinMcClure 9/22/2012 16:09",
+		"assignOutputVariableAvoiding:" : "MartinMcClure 9/29/2012 12:18",
+		"emitOpTo:" : "MartinMcClure 9/29/2012 12:33",
 		"label" : "MartinMcClure 9/22/2012 16:08" } }
diff --git a/packages/Mist.package/FogX64Node.class/instance/addOwnClobberedTo..st b/packages/Mist.package/FogX64Node.class/instance/addOwnClobberedTo..st
@@ -1,6 +1,6 @@
 x64-compiling-pass1
 addOwnClobberedTo: aClobberedSet
 
-	"If my own execution uses or clobbers any locations other than my own input and output variables, or the scratch registers rax, rbx, and r11,, add those to the given clobbered set. Must add any scratch registers that I *might* use."
+	"If my own execution uses or clobbers any locations other than my own input and output variables, other than the scratch registers rax, rbx, and r11, add those to the given clobbered set."
 
 	"Many nodes do not clobber anything"
diff --git a/packages/Mist.package/FogX64Node.class/methodProperties.json b/packages/Mist.package/FogX64Node.class/methodProperties.json
@@ -24,7 +24,7 @@
 		"variableScope:steps:" : "MartinMcClure 12/24/2010 14:54" },
 	"instance" : {
 		"addChild:" : "MartinMcClure 11/15/2010 21:48",
-		"addOwnClobberedTo:" : "MartinMcClure 11/4/2011 10:38",
+		"addOwnClobberedTo:" : "MartinMcClure 9/29/2012 11:37",
 		"assignDeclaredVariablesAvoiding:" : "MartinMcClure 12/25/2010 19:16",
 		"assignInputVariableNumber:" : "MartinMcClure 8/26/2011 06:25",
 		"assignOutputVariableAvoiding:" : "MartinMcClure 8/26/2011 00:24",

diff --git a/...Mist.package/X64CodeStream.class/instance/movByteFromAddressIn.plusIndexIn.toRegister..st b/...Mist.package/X64CodeStream.class/instance/movByteFromAddressIn.plusIndexIn.toRegister..st
@@ -1,6 +1,7 @@
 instructions
 movByteFromAddressIn: baseReg plusIndexIn: indexReg toRegister: destReg
-	"A mov instruction to fetch 8 bits of memory from the address in baseReg, indexed by indexReg, and put those 64 bits in destReg. All three arguments must be register locations."
+	"A mov instruction to fetch 8 bits of memory from the address in baseReg, byte-indexed by indexReg, and put those 64 bits in destReg. 
+	All three arguments must be register locations."
 
 	| rex modRm sib |
 	(destReg isRegister and: [ baseReg isRegister and: [ indexReg isRegister ] ])
@@ -13,5 +14,5 @@ movByteFromAddressIn: baseReg plusIndexIn: indexReg toRegister: destReg
 	output nextPut: 16r8A.	"opcode"
 	modRm := destReg lowNumber * 8 + 4.
 	output nextPut: modRm.
-	sib := 16rC0 + (indexReg lowNumber * 8) + baseReg lowNumber.	"scale is 3 for 64-bit indexing"
+	sib := indexReg lowNumber * 8 + baseReg lowNumber.	"scale is 0 for 8-bit indexing"
 	output nextPut: sib
diff --git a/packages/Mist.package/X64CodeStream.class/methodProperties.json b/packages/Mist.package/X64CodeStream.class/methodProperties.json
@@ -18,7 +18,7 @@
 		"jmpTo:" : "MartinMcClure 9/28/2012 22:45",
 		"label:" : "MartinMcClure 9/28/2012 22:36",
 		"labelAt:" : "MartinMcClure 9/28/2012 22:35",
-		"movByteFromAddressIn:plusIndexIn:toRegister:" : "MartinMcClure 9/22/2012 17:11",
+		"movByteFromAddressIn:plusIndexIn:toRegister:" : "MartinMcClure 9/29/2012 11:22",
 		"movByteFromRegister:toAddressIn:plusIndexIn:" : "MartinMcClure 11/5/2011 08:46",
 		"movFrom:to:" : "MartinMcClure 11/6/2011 16:19",
 		"movFromAddressIn:plusIndexIn:toRegister:" : "MartinMcClure 11/6/2011 16:32",

diff --git a/packages/Mist.package/X64DisassemblerDisp32Operand.class/README.md b/packages/Mist.package/X64DisassemblerDisp32Operand.class/README.md
@@ -0,0 +1,6 @@
+A X64DisassemblerDisp32Operand is a 32-bit RIP-relative signed displacement, not associated with a SIB byte. 
+In 64-bit mode (the only mode used by Mist) this appears in only JMP and Jcc instructions.
+
+Instance Variables:
+	bytesSoFar	<Integer> How many of the four displacement bytes have been received so far
+	displacementValue	<Integer> The accumulated value. This will be unsigned until the last byte is received, at which point it may be discovered that it should be negative and adjusted.
diff --git a/packages/Mist.package/X64DisassemblerDisp32Operand.class/instance/dispByte..st b/packages/Mist.package/X64DisassemblerDisp32Operand.class/instance/dispByte..st
@@ -0,0 +1,9 @@
+instruction byte handling
+dispByte: byte
+	"Displacement bytes are little-endian, so each byte received is of greater significance than all received so far."
+
+	displacementValue := displacementValue + (byte bitShift: bytesSoFar * 8).
+	bytesSoFar := bytesSoFar + 1.	
+	"If we've received the last byte, we can now convert value from unsigned to signed."
+	(bytesSoFar = 4 and: [ displacementValue > 16r7FFFFFFF ])
+		ifTrue: [ displacementValue := displacementValue - 16r100000000 ]
diff --git a/packages/Mist.package/X64DisassemblerDisp32Operand.class/instance/informDisplacement.st b/packages/Mist.package/X64DisassemblerDisp32Operand.class/instance/informDisplacement.st
@@ -0,0 +1,5 @@
+private
+informDisplacement
+	"I am an operand that involves a non-SIB displacement, so let my instruction know how many displacement bytes to expect."
+
+	instruction displacementSize: 4
diff --git a/packages/Mist.package/X64DisassemblerDisp32Operand.class/instance/informModRM.st b/packages/Mist.package/X64DisassemblerDisp32Operand.class/instance/informModRM.st
@@ -0,0 +1,6 @@
+private
+informModRM
+	"If this operand requires a ModRM byte, tell my instruction.
+	JMP and Jcc don't, so do nothing."
+
+
diff --git a/packages/Mist.package/X64DisassemblerDisp32Operand.class/instance/initialize.st b/packages/Mist.package/X64DisassemblerDisp32Operand.class/instance/initialize.st
@@ -0,0 +1,3 @@
+initialize-release
+initialize
+	bytesSoFar := displacementValue := 0
diff --git a/packages/Mist.package/X64DisassemblerDisp32Operand.class/instance/printOn..st b/packages/Mist.package/X64DisassemblerDisp32Operand.class/instance/printOn..st
@@ -0,0 +1,6 @@
+printing
+printOn: stream
+	| targetAddress |
+	targetAddress := instruction nextInstructionAddress + displacementValue.
+	stream nextPutAll: '0x'.
+	targetAddress printOn: stream base: 16
diff --git a/packages/Mist.package/X64DisassemblerDisp32Operand.class/methodProperties.json b/packages/Mist.package/X64DisassemblerDisp32Operand.class/methodProperties.json
@@ -0,0 +1,9 @@
+{
+	"class" : {
+		 },
+	"instance" : {
+		"dispByte:" : "MartinMcClure 9/29/2012 10:52",
+		"informDisplacement" : "MartinMcClure 9/29/2012 10:57",
+		"informModRM" : "MartinMcClure 9/29/2012 10:48",
+		"initialize" : "MartinMcClure 9/29/2012 10:35",
+		"printOn:" : "MartinMcClure 9/29/2012 10:44" } }
diff --git a/packages/Mist.package/X64DisassemblerDisp32Operand.class/properties.json b/packages/Mist.package/X64DisassemblerDisp32Operand.class/properties.json
@@ -0,0 +1,15 @@
+{
+	"category" : "Mist",
+	"classinstvars" : [
+		 ],
+	"classvars" : [
+		 ],
+	"commentStamp" : "MartinMcClure 9/29/2012 10:34",
+	"instvars" : [
+		"bytesSoFar",
+		"displacementValue" ],
+	"name" : "X64DisassemblerDisp32Operand",
+	"pools" : [
+		 ],
+	"super" : "X64DisassemblerOperand",
+	"type" : "normal" }
diff --git a/packages/Mist.package/X64DisassemblerInstruction.class/instance/Jz.st b/packages/Mist.package/X64DisassemblerInstruction.class/instance/Jz.st
@@ -0,0 +1,6 @@
+address modes sent by perform:
+Jz
+	"Op mode Jz, RIP-relative 32-bit displacement.
+	Mist doesn't use the 16-bit version of Jz, so we only deal with the 32-bit one here."
+
+	operands add: (X64DisassemblerDisp32Operand forInstruction: self)
diff --git a/packages/Mist.package/X64DisassemblerInstruction.class/instance/nextInstructionAddress.st b/packages/Mist.package/X64DisassemblerInstruction.class/instance/nextInstructionAddress.st
@@ -0,0 +1,6 @@
+accessing
+nextInstructionAddress
+	"Warning: This message will not give the correct answer until all bytes for the instruction have been processed.
+	It is intended to be used during the instruction printing phase."
+
+	^ startAddress + bytes size
diff --git a/packages/Mist.package/X64DisassemblerInstruction.class/methodProperties.json b/packages/Mist.package/X64DisassemblerInstruction.class/methodProperties.json
@@ -7,6 +7,7 @@
 		"Gb" : "MartinMcClure 9/11/2012 01:40",
 		"Gv" : "MartinMcClure 9/10/2012 19:33",
 		"Iv" : "MartinMcClure 9/7/2012 08:54",
+		"Jz" : "MartinMcClure 9/29/2012 10:55",
 		"bBit" : "MartinMcClure 9/10/2012 19:22",
 		"bBit:" : "MartinMcClure 3/22/2012 11:47",
 		"defaultOpSizeIs64:" : "MartinMcClure 9/7/2012 06:04",
@@ -25,6 +26,7 @@
 		"isByteOpMode:" : "MartinMcClure 9/7/2012 06:29",
 		"mnemonic:" : "MartinMcClure 9/2/2012 02:59",
 		"modRMByte:" : "MartinMcClure 9/10/2012 19:26",
+		"nextInstructionAddress" : "MartinMcClure 9/29/2012 10:46",
 		"nextOpcodeMap:" : "MartinMcClure 9/2/2012 22:40",
 		"opcodeByte:" : "MartinMcClure 2/13/2012 13:23",
 		"plusR" : "MartinMcClure 9/10/2012 07:32",

diff --git a/packages/Mist.package/X64DisassemblerOpcodeMapPrimary.class/instance/initialize.st b/packages/Mist.package/X64DisassemblerOpcodeMapPrimary.class/instance/initialize.st
@@ -12,7 +12,6 @@ initialize
 		atAllFrom: 16r28 to: 16r2D putMnemonic: 'sub';
 		atAllFrom: 16r30 to: 16r35 putMnemonic: 'xor';
 		atAllFrom: 16r38 to: 16r3D putMnemonic: 'cmp'.
-
 	self
 		atAllFrom: 16r00
 			to: 16r38
@@ -42,4 +41,7 @@ initialize
 		initializeRexPrefixes;
 		initialize8LineMovs;
 		initializeBLineMovs;
-		initializeCLine
+		initializeCLine.
+	self
+		at: 16rE9 putMnemonic: 'jmp';
+		at: 16rE9 putOperandTypes: #(#Jz)
diff --git a/packages/Mist.package/X64DisassemblerOpcodeMapPrimary.class/methodProperties.json b/packages/Mist.package/X64DisassemblerOpcodeMapPrimary.class/methodProperties.json
@@ -4,7 +4,7 @@
 		"singleton" : "MartinMcClure 1/9/2012 21:25" },
 	"instance" : {
 		"actionFor:repePrefix:repnePrefix:addrSizePrefix:" : "MartinMcClure 2/13/2012 17:35",
-		"initialize" : "MartinMcClure 9/3/2012 11:57",
+		"initialize" : "MartinMcClure 9/29/2012 11:02",
 		"initialize8LineMovs" : "MartinMcClure 9/3/2012 12:01",
 		"initializeBLineMovs" : "MartinMcClure 9/9/2012 22:51",
 		"initializeCLine" : "MartinMcClure 9/2/2012 06:20",

diff --git a/packages/Mist.package/X64DisassemblerOperand.class/class/forInstruction..st b/packages/Mist.package/X64DisassemblerOperand.class/class/forInstruction..st
@@ -5,5 +5,6 @@ forInstruction: instruction
 	inst instruction: instruction.
 	inst
 		informModRM;
+		informDisplacement;
 		informImmediate.
 	^ inst
diff --git a/packages/Mist.package/X64DisassemblerOperand.class/instance/informDisplacement.st b/packages/Mist.package/X64DisassemblerOperand.class/instance/informDisplacement.st
@@ -0,0 +1,4 @@
+private
+informDisplacement
+	"If I am a pure displacement operand, let my instruction know how many displacement bytes to expect.
+	Default is to not be an displacement operand, overridden in displacement subclass, so do nothing here."
diff --git a/packages/Mist.package/X64DisassemblerOperand.class/methodProperties.json b/packages/Mist.package/X64DisassemblerOperand.class/methodProperties.json
@@ -1,11 +1,12 @@
 {
 	"class" : {
-		"forInstruction:" : "MartinMcClure 9/7/2012 09:10",
+		"forInstruction:" : "MartinMcClure 9/29/2012 10:26",
 		"initialize" : "MartinMcClure 9/5/2012 02:07",
 		"initializeRegisterNames" : "MartinMcClure 9/5/2012 02:06" },
 	"instance" : {
 		"dispByte:" : "MartinMcClure 9/12/2012 04:45",
 		"immediateByte:" : "MartinMcClure 9/9/2012 23:42",
+		"informDisplacement" : "MartinMcClure 9/29/2012 10:27",
 		"informImmediate" : "MartinMcClure 9/7/2012 09:16",
 		"informModRM" : "MartinMcClure 9/10/2012 07:23",
 		"instruction:" : "MartinMcClure 9/5/2012 02:16",

diff --git a/packages/Mist.package/X64DisassemblerTests.class/instance/testIsB.st b/packages/Mist.package/X64DisassemblerTests.class/instance/testIsB.st
@@ -6,4 +6,80 @@ testIsB
 	self
 		assert: disassembly
 		equals:
-			''
+'000000400078: 48 BD 00 00 50 00 00 00 00 00                mov     rbp,0x500000
+000000400082: 49 BE 10 00 00 00 00 00 00 00                mov     r14,0x10
+00000040008C: 48 BF 00 00 00 00 00 00 00 00                mov     rdi,0x0
+000000400096: 48 BE 00 10 00 00 00 00 00 00                mov     rsi,0x1000
+0000004000A0: 48 BA 03 00 00 00 00 00 00 00                mov     rdx,0x3
+0000004000AA: 49 BA 22 00 00 00 00 00 00 00                mov     r10,0x22
+0000004000B4: 49 B8 FF FF FF FF FF FF FF FF                mov     r8,0xFFFFFFFFFFFFFFFF
+0000004000BE: 49 B9 00 00 00 00 00 00 00 00                mov     r9,0x0
+0000004000C8: 48 B8 09 00 00 00 00 00 00 00                mov     rax,0x9
+0000004000D2: 0F 05                                        syscall 
+0000004000D4: 49 89 C7                                     mov     r15,rax
+0000004000D7: 4C 89 BD F0 FF FF FF                         mov     [rbp-0x10],r15
+0000004000DE: 4D 01 F7                                     add     r15,r14
+0000004000E1: 4C 89 BD F8 FF FF FF                         mov     [rbp-0x8],r15
+0000004000E8: 48 BF 00 00 00 00 00 00 00 00                mov     rdi,0x0
+0000004000F2: 48 BE 01 54 00 00 00 00 00 00                mov     rsi,0x5401
+0000004000FC: 48 8B 95 F8 FF FF FF                         mov     rdx,[rbp-0x8]
+000000400103: 48 B8 10 00 00 00 00 00 00 00                mov     rax,0x10
+00000040010D: 0F 05                                        syscall 
+00000040010F: 4C 8B 95 F8 FF FF FF                         mov     r10,[rbp-0x8]
+000000400116: 49 BC 01 00 00 00 00 00 00 00                mov     r12,0x1
+000000400120: 49 BD FF FF FF FF F5 FF FF FF                mov     r13,0xFFFFFFF5FFFFFFFF
+00000040012A: 4C 8B B5 F8 FF FF FF                         mov     r14,[rbp-0x8]
+000000400131: 49 BF 01 00 00 00 00 00 00 00                mov     r15,0x1
+00000040013B: 4F 8B 3C FE                                  mov     r15,[r14+r15*8]
+00000040013F: 4D 21 EF                                     and     r15,r13
+000000400142: 4F 89 3C E2                                  mov     [r10+r12*8],r15
+000000400146: 48 BF 00 00 00 00 00 00 00 00                mov     rdi,0x0
+000000400150: 48 BE 02 54 00 00 00 00 00 00                mov     rsi,0x5402
+00000040015A: 48 8B 95 F8 FF FF FF                         mov     rdx,[rbp-0x8]
+000000400161: 48 B8 10 00 00 00 00 00 00 00                mov     rax,0x10
+00000040016B: 0F 05                                        syscall 
+00000040016D: 48 BF 00 00 00 00 00 00 00 00                mov     rdi,0x0
+000000400177: 48 8B B5 F0 FF FF FF                         mov     rsi,[rbp-0x10]
+00000040017E: 48 BA 01 00 00 00 00 00 00 00                mov     rdx,0x1
+000000400188: 48 B8 00 00 00 00 00 00 00 00                mov     rax,0x0
+000000400192: 0F 05                                        syscall 
+000000400194: 4C 8B 95 F8 FF FF FF                         mov     r10,[rbp-0x8]
+00000040019B: 49 BC 01 00 00 00 00 00 00 00                mov     r12,0x1
+0000004001A5: 49 BD 00 00 00 00 0A 00 00 00                mov     r13,0xA00000000
+0000004001AF: 4C 8B B5 F8 FF FF FF                         mov     r14,[rbp-0x8]
+0000004001B6: 49 BF 01 00 00 00 00 00 00 00                mov     r15,0x1
+0000004001C0: 4F 8B 3C FE                                  mov     r15,[r14+r15*8]
+0000004001C4: 4D 09 EF                                     or      r15,r13
+0000004001C7: 4F 89 3C E2                                  mov     [r10+r12*8],r15
+0000004001CB: 48 BF 00 00 00 00 00 00 00 00                mov     rdi,0x0
+0000004001D5: 48 BE 02 54 00 00 00 00 00 00                mov     rsi,0x5402
+0000004001DF: 48 8B 95 F8 FF FF FF                         mov     rdx,[rbp-0x8]
+0000004001E6: 48 B8 10 00 00 00 00 00 00 00                mov     rax,0x10
+0000004001F0: 0F 05                                        syscall 
+0000004001F2: 4C 8B B5 F0 FF FF FF                         mov     r14,[rbp-0x10]
+0000004001F9: 49 BF 00 00 00 00 00 00 00 00                mov     r15,0x0
+000000400203: 49 BD 00 00 00 00 00 00 00 00                mov     r13,0x0
+00000040020D: 47 8A 2C 3E                                  mov     r13b,[r14+r15*1]
+000000400211: 49 BF 42 00 00 00 00 00 00 00                mov     r15,0x42
+00000040021B: 4D 39 EF                                     cmp     r15,r13
+00000040021E: 0F 85 24 00 00 00                            jnz     0x400248
+000000400224: 4C 8B A5 F0 FF FF FF                         mov     r12,[rbp-0x10]
+00000040022B: 49 BE 01 00 00 00 00 00 00 00                mov     r14,0x1
+000000400235: 49 BF 54 00 00 00 00 00 00 00                mov     r15,0x54
+00000040023F: 47 88 3C 34                                  mov     [r12+r14*1],r15b
+000000400243: E9 1F 00 00 00                               jmp     0x400267
+000000400248: 4C 8B A5 F0 FF FF FF                         mov     r12,[rbp-0x10]
+00000040024F: 49 BE 01 00 00 00 00 00 00 00                mov     r14,0x1
+000000400259: 49 BF 46 00 00 00 00 00 00 00                mov     r15,0x46
+000000400263: 47 88 3C 34                                  mov     [r12+r14*1],r15b
+000000400267: 48 BF 01 00 00 00 00 00 00 00                mov     rdi,0x1
+000000400271: 4C 8B BD F0 FF FF FF                         mov     r15,[rbp-0x10]
+000000400278: 48 BE 01 00 00 00 00 00 00 00                mov     rsi,0x1
+000000400282: 4C 01 FE                                     add     rsi,r15
+000000400285: 48 BA 01 00 00 00 00 00 00 00                mov     rdx,0x1
+00000040028F: 48 B8 01 00 00 00 00 00 00 00                mov     rax,0x1
+000000400299: 0F 05                                        syscall 
+00000040029B: 48 BF 00 00 00 00 00 00 00 00                mov     rdi,0x0
+0000004002A5: 48 B8 E7 00 00 00 00 00 00 00                mov     rax,0xE7
+0000004002AF: 0F 05                                        syscall 
+'
diff --git a/packages/Mist.package/X64DisassemblerTests.class/methodProperties.json b/packages/Mist.package/X64DisassemblerTests.class/methodProperties.json
@@ -6,7 +6,7 @@
 		"testConsume1" : "MartinMcClure 9/13/2012 17:34",
 		"testEcho1" : "MartinMcClure 9/13/2012 17:29",
 		"testFortyTwo" : "MartinMcClure 9/13/2012 17:22",
-		"testIsB" : "MartinMcClure 9/22/2012 14:30",
+		"testIsB" : "MartinMcClure 9/29/2012 12:32",
 		"testPrint7" : "MartinMcClure 9/13/2012 17:28",
 		"testPrintH" : "MartinMcClure 9/13/2012 17:25",
 		"testThreePlusFour" : "MartinMcClure 9/13/2012 17:24" } }
diff --git a/packages/Mist.package/monticello.meta/version b/packages/Mist.package/monticello.meta/version