FFT-OFDM-receiver

Input signal was generated by software simulation and was demodulated by PYNQ-Z2 hardware.

OFDM receiver block diagram

We implement the red block through RTL coding

We adopt Radix-2 DIT FFT algorithm, butterfly unit

Vivado block design

Resource usage

OFDM reciever architecture with 16 point Radix-2 DIT FFT - work! OFDM reciever architecture with 32 point Radix-2 DIT FFT - slices of DSP is not enough in this PYNQ-Z2 board Although we still can implement 32 point FFT with strategies, we do not have time to fix all the bugs during term project.

Precision consideration

To specify porper fractional bits on FPGA outcome, we simulate hexadecimal digits on Bit Error Rate (BER) performance corresponding to Signal to Noise Ratio (SNR). To achieve a reasonable result, we use two hex digits as the fractional part.

System behavior flowchart

Vitis output

Input 120 transmitted data with SNR=10 (6 symbols, 20 transmitted data for each symbol)
Compare data with the golden model simulated by MATLAB
Zero errors between PYNQ-Z2 hardware and Matlab result

Input 1000 OFDM symbols with SNR=10 (20 transmitted data for each symbol)
Same with Matlab simulation

Input 1000 OFDM symbols with SNR=1 (20 transmitted data for each symbol)
Demodulated data maintained 99.6% accuracy