GitHub - matheuscandido/MIPSVerilog: Basic implementation of a MIPS microprocessor on Verilog and Intel Max 10 FPGA family.

Name		Name	Last commit message	Last commit date
Latest commit History 44 Commits
ALU		ALU
AddressDecoder		AddressDecoder
DataMemory		DataMemory
InstructionMemory		InstructionMemory
Multiplicador		Multiplicador
PC		PC
PLL		PLL
Register		Register
busController		busController
control		control
db		db
extend		extend
mux		mux
output_files		output_files
registerFile		registerFile
.gitignore		.gitignore
cpu.qpf		cpu.qpf
cpu.qsf		cpu.qsf
cpu.sdc		cpu.sdc
cpu.v		cpu.v
cpu.v.bak		cpu.v.bak
cpu_TB.v		cpu_TB.v
cpu_assignment_defaults.qdf		cpu_assignment_defaults.qdf