Set CACHE_LINE_SIZE to 128 for __powerpc64__, and 256 for __s390x__.

max0x7ba · Oct 20, 2021 · f2a36a3 · f2a36a3
1 parent ee3d91c
commit f2a36a3
Showing 1 changed file with 6 additions and 1 deletion.
diff --git a/include/atomic_queue/defs.h b/include/atomic_queue/defs.h
@@ -37,11 +37,16 @@ static inline void spin_loop_pause() noexcept {
 } // namespace atomic_queue
 #elif defined(__ppc64__) || defined(__powerpc64__)
 namespace atomic_queue {
-constexpr int CACHE_LINE_SIZE = 64; // TODO: Review that this is the correct value.
+constexpr int CACHE_LINE_SIZE = 128; // TODO: Review that this is the correct value.
 static inline void spin_loop_pause() noexcept {
     asm volatile("or 31,31,31 # very low priority"); // TODO: Review and benchmark that this is the right instruction.
 }
 } // namespace atomic_queue
+#elif defined(__s390x__)
+namespace atomic_queue {
+constexpr int CACHE_LINE_SIZE = 256; // TODO: Review that this is the correct value.
+static inline void spin_loop_pause() noexcept {} // TODO: Find the right instruction to use here, if any.
+} // namespace atomic_queue
 #else
 #warning "Unknown CPU architecture. Using L1 cache line size of 64 bytes and no spinloop pause instruction."
 namespace atomic_queue {