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This repository has been archived by the owner on Jun 26, 2023. It is now read-only.

max6cn/verilogplugin

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Notice

Due to a FS crash most progress has been lost, this project has been paused until further notice

Verilogplugin

Verilog Plugin for Intellij IDEA

Status

  • working on lexer and basic syntax highlighter
  • parser

Features(Planed)

  • Lexer
  • Syntax Highlighting
  • Parser
  • Anotator
  • External Tool
  • Color settings
  • Refrences and resolve
  • Code completion Reference completion contributor-based completion
  • Find Usages
  • Rename Refactoring
  • Safe Delete Refactoring
  • Code Formatter
  • Code Style Setting
  • Rearranger
  • Code Inspections and Intentions
  • Structure View
  • Surround With
  • Goto and Goto Symbol
  • Indexing
  • Stub Trees
  • Documentation
  • Minor Features code folding Coment Code Join Lines Smart Enter Naming suggestions Sematic highlight usage View |Parameter Info To Do View View |Conext info Spellchecking

3rd Party Tool Support

  • Synthesis Tools Support(include FPGA)
  • Simulation tools Support
  • Linter
  • Waveform Viewer(?)
  • Blockdiagram viewer(?)