Add B_U585_IOT02A upload method support and default OSPIF mappings. G…

…uard against incorrect case on upload method

storage/blockdevice/COMPONENT_OSPIF/mbed_lib.json

@@ -28,6 +28,19 @@
     "target_overrides": {
         "MX25LM51245G": {
             "OSPI_FREQ": "66000000"
+        },
+        "B_U585_IOT02A": {
+            "OSPI_IO0": "PF_0",
+            "OSPI_IO1": "PF_1",
+            "OSPI_IO2": "PF_2",
+            "OSPI_IO3": "PF_3",
+            "OSPI_IO4": "PH_9",
+            "OSPI_IO5": "PH_10",
+            "OSPI_IO6": "PH_11",
+            "OSPI_IO7": "PH_12",
+            "OSPI_SCK": "PF_4",
+            "OSPI_CSN": "PI_5",
+            "OSPI_DQS": "PF_12"
         }
     }
 }

targets/upload_method_cfg/B_U585I_IOT02A.cmake

@@ -0,0 +1,47 @@
+# Mbed OS upload method configuration file for target B_U585_IOT02A.
+# To change any of these parameters from their default values, set them in your build script between where you
+# include app.cmake and where you add mbed os as a subdirectory.
+
+# Notes:
+# 1. To use this target with PyOCD, you need to install a pack: `pyocd pack install STM32U585AIIxQ`.
+#    You might also need to run `pyocd pack update` first.
+
+# General config parameters
+# -------------------------------------------------------------
+set(UPLOAD_METHOD_DEFAULT MBED)
+
+# Config options for MBED
+# -------------------------------------------------------------
+
+set(MBED_UPLOAD_ENABLED TRUE)
+set(MBED_RESET_BAUDRATE 115200)
+
+# Config options for PYOCD
+# -------------------------------------------------------------
+
+set(PYOCD_UPLOAD_ENABLED TRUE)
+set(PYOCD_TARGET_NAME STM32U585AIIxQ)
+set(PYOCD_CLOCK_SPEED 4000k)
+
+# Config options for OPENOCD
+# -------------------------------------------------------------
+
+set(OPENOCD_UPLOAD_ENABLED TRUE)
+set(OPENOCD_CHIP_CONFIG_COMMANDS
+    -f ${OpenOCD_SCRIPT_DIR}/interface/stlink.cfg
+	-c "transport select hla_swd"
+	-f ${CMAKE_CURRENT_LIST_DIR}/openocd_cfgs/stm32u5x.cfg)
+
+# Config options for STM32Cube
+# -------------------------------------------------------------
+
+set(STM32CUBE_UPLOAD_ENABLED TRUE)
+set(STM32CUBE_CONNECT_COMMAND -c port=SWD reset=HWrst)
+set(STM32CUBE_GDBSERVER_ARGS --swd)
+
+# Config options for stlink
+# -------------------------------------------------------------
+
+set(STLINK_UPLOAD_ENABLED TRUE)
+set(STLINK_LOAD_ADDRESS 0x8000000)
+set(STLINK_ARGS --connect-under-reset)

targets/upload_method_cfg/openocd_cfgs/stm32u5x.cfg

@@ -0,0 +1,58 @@
+# From: https://github.com/STMicroelectronics/OpenOCD/blob/openocd-cubeide-r6/tcl/target/stm32u5x.cfg
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32u5x family
+# stm32u5x devices support both JTAG and SWD transports.
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32u5x
+}
+
+source [find target/stm32x5x_common.cfg]
+
+proc stm32u5x_clock_config {} {
+	set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
+	# MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL
+
+	# Enable voltage range 1 for frequency above 100 Mhz
+	# RCC_AHB3ENR = PWREN
+	mww [expr {0x46020C94 + $offset}] 0x00000004
+	# delay for register clock enable (read back reg)
+	mrw [expr {0x46020C94 + $offset}]
+	# PWR_VOSR : VOS Range 1
+	mmw [expr {0x4602080C + $offset}] 0x00030000 0
+	# while !(PWR_VOSR & VOSRDY)
+	while {!([mrw [expr {0x4602080C + $offset}]] & 0x00008000)} {}
+	# FLASH_ACR : 4 WS for 160 MHz HCLK
+	mww [expr {0x40022000 + $offset}] 0x00000004
+	# RCC_PLL1CFGR => PLL1MBOOST=0, PLL1M=0=/1, PLL1FRACEN=0, PLL1SRC=MSI 4MHz
+	#                 PLL1REN=1, PLL1RGE => VCOInputRange=PLLInputRange_4_8
+	mww [expr {0x46020C28 + $offset}] 0x00040009
+	# Enable EPOD Booster
+	mmw [expr {0x4602080C + $offset}] 0x00040000 0
+	# while !(PWR_VOSR & BOOSTRDY)
+	while {!([mrw [expr {0x4602080C + $offset}]] & 0x00004000)} {}
+	# RCC_PLL1DIVR => PLL1P=PLL1Q=PLL1R=000001=/2, PLL1N=0x4F=80
+	# fVCO = 4 x 80 /1 = 320
+	# SYSCLOCK = fVCO/PLL1R = 320/2 = 160 MHz
+	mww [expr {0x46020C34 + $offset}] 0x0101024F
+	# RCC_CR |= PLL1ON
+	mmw [expr {0x46020C00 + $offset}] 0x01000000 0
+	# while !(RCC_CR & PLL1RDY)
+	while {!([mrw [expr {0x46020C00 + $offset}]] & 0x02000000)} {}
+	# RCC_CFGR1 |= SW_PLL
+	mmw [expr {0x46020C1C + $offset}] 0x00000003 0
+	# while ((RCC_CFGR1 & SWS) != PLL)
+	while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32u5x_clock_config
+	# Boost JTAG frequency
+	adapter speed 4000
+}

tools/cmake/UploadMethodManager.cmake

@@ -14,6 +14,14 @@ set(UPLOAD_METHOD "${UPLOAD_METHOD_DEFAULT}" CACHE STRING "Method for uploading
 # use a higher numbered port to allow use without root on Linux/Mac
 set(GDB_PORT 23331 CACHE STRING "Port that the GDB server will be started on.")
 
+# Upload methods must be uppercase, guard against the user making a mistake (since Windows will allow opening
+# an include file with the wrong case, the error message gets confusing)
+string(TOUPPER "${UPLOAD_METHOD}" UPLOAD_METHOD_UCASE)
+if(NOT "${UPLOAD_METHOD_UCASE}" STREQUAL "${UPLOAD_METHOD}")
+	message(WARNING "UPLOAD_METHOD value should be uppercase.  It has been automatically changed to \"${UPLOAD_METHOD_UCASE}\".")
+	set(UPLOAD_METHOD "${UPLOAD_METHOD_UCASE}" CACHE STRING "" FORCE)
+endif()
+
 # Load the upload method.  This is expected to set the following variables:
 # UPLOAD_${UPLOAD_METHOD}_FOUND - True iff the dependencies for this upload method were found
 # UPLOAD_SUPPORTS_DEBUG - True iff this upload method supports debugging